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preliminary data sheet bcm5220 5220-ds04-405-r 16215 alton parkway ? p.o. box 57013 irvine, ca 92619-7013 phone: 949-450-8700 fax: 949-450-8710 04/20/04 10/100base-tx/fx mini- ? transceiver figure 1: functional block diagram g eneral description f eatures the bcm5220 is a single channel, low-power, 10/ 100base-tx/fx transceiver targeting a number of applications requiring intelligent power management and robust network tolerance. the bcm5220 operates at 3.3v or 2.5v. the devices contain a full-duplex 10base- t/100base-tx/100base-fx fast ethernet transceiver, which performs all of the physical layer interface functions for 10base-t ethernet on cat 3, 4, and 5 unshielded twisted pair (utp) cable and 100base-tx fast ethernet on cat 5 utp cable. in addition, pin-compatibility with the bcm5221 offers the flexibility of an upgrade path. 100base-fx is supported through the use of external fiber-optic transmit and receive devices. the bcm5220 is a highly integrated solution combining a digital adaptive equalizer, adc, phase lock loop, line driver, encoder, decoder and all the required support circuitry into a single monolithic cmos chip. it complies fully with the ieee 802.3u specification, including the media independent interface (mii) and auto-negotiation subsections. the effective use of digital technology in the bcm5220 design results in robust performance over a broad range of operating scenarios. problems inherent to mixed- signal implementations, such as analog offset and on- chip noise, are eliminated by employing field proven digital adaptive equalization and digital clock recovery techniques. power supply: 2.5v or 3.3v integrated voltage regulator to allow operation from a single supply source power consumption: <275 mw unique energy detection circuit to enable intelligent power management cable length indication cable noise level indication robust cesd tolerance cable length greater than 140 meters well under 10 ppm defect ratio quality +10% voltage tolerance industrial temperature range (-40 to 85c) mii and 7-wire serial interface configurable ieee 1149.1 (jtag) scan chain support mii management via serial port pin-compatible with bcm5221 10base-t/100base-tx/fx ieee 802.3u fast ethernet transceiver 64-pin tqfp or 64-pin bga package a pplications pcmcia/cardbus cards lan on motherboard ip phones cable modems set-top boxes and print servers wireless access points embedded telecom adc
broadcom corporation p.o. box 57013 16215 alton parkway irvine, ca 92619-7013 ? 2004 by broadcom corporation all rights reserved printed in the u.s.a. broadcom ? and the pulse logo are registered trademarks of bro adcom corporation and/or its subsidiaries in the united states and certain other countries. all other trademarks mentioned are the property of their respective owners. this data sheet (including, without limitation, the broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high risk application. broadcom provides this data sheet "as- is", without warranty of any kind. broadcom disclaims all warranties, expressed and implied, including, without limitation, the im plied warranties of merchantability, fitness for a particular purpose, and non-infringement. r evision h istory revision # date change description 5520-ds04-405-r 04/20/04 added rmii timing information to ?timing and ac characteristics? on page 58. 5220-ds03-r 09/30/02 replaced functional block diagram on cover page. modified various function descriptions in table 3. modified various function descriptions in table 9. modified various values in table 37. deleted tables 50 through 53. deleted figures 17 and 18. 5220-ds02-r 05/25/01 page 14, 17 and 49 - clarified power on reset requirement. page 10 pin descriptions- added sentence to pin h8 and g8. page 16 - added separate 100base-tx and 10base link sentence to special led modes. page 21 - added alt link mode to bit 12 of auxiliary mode in table 7. page 42 - added bits 11:5, and 12 to table 28. 5220-ds01-r 03/02/01 eliminated xtalvdd references. changed advanced specifications to preliminary specifications. deleted ck25 from phyad4. removed txdac power mode bit from mii registers 18h bit 8, table 7. changed default value of mii register 1ah, table 7. added bit 15, fdx led enable to mii register 1ah, table 25. fixed several register definitions and moved them to correct tables. added timing and power values to parameters in table 40 through 57. added thermal characteristics section. updated table 57, electrical characteristics. updated pin label descriptions for xtali/xtalo and energy_det in table 3. updated phy identifier registers section by changing 00h to 0h in paragraph under table 11. updated descriptions for leds h8 and g8 in table 3, pin descriptions. 5220-ds00-r 10/01/00 initial release.
broadcom corporation document 5220-ds04-405-r page iii preliminary data sheet bcm5220 04/20/04 t able of c ontents section 1: functional description ...................................................................................... 1 overview ............................................................................................................................... ........................ 1 encoder/decoder ............................................................................................................................... .......... 1 link monitor ............................................................................................................................... ................... 2 carrier sense ............................................................................................................................... ................. 2 collision detection ............................................................................................................................... ........ 2 digital adaptive equalizer ........................................................................................................................... 3 adc ............................................................................................................................... ................................ 3 digital clock recovery/generator .............................................................................................................. 3 multimode transmit dac ............................................................................................................................ 4 stream cipher ............................................................................................................................... ................ 4 far-end fault ............................................................................................................................... ................. 5 mii management ............................................................................................................................... ............ 5 section 2: hardware signal definition table ..................................................................... 7 section 3: pinout diagram ................................................................................................11 section 4: operational description ..................................................................................13 reset ............................................................................................................................... ............................ 13 isolate mode ............................................................................................................................... ................ 13 loopback mode ............................................................................................................................... ........... 13 full-duplex mode ............................................................................................................................... ........ 14 100base-fx mode ............................................................................................................................... ...... 14 10base-t mode ............................................................................................................................... .......... 14 10base-t serial mode ............................................................................................................................... 14 special led modes ............................................................................................................................... ..... 15 traffic meter mode............................................................................................................. ............ 15 force leds on .................................................................................................................. ............ 15 disable leds ................................................................................................................... .............. 15 separate 100base-tx and 10-base-t link ................................................................................ 15 energy detection ............................................................................................................................... ......... 16 auto power-down mode ............................................................................................................................ 17
broadcom corporation page iv document 5220-ds04-405-r bcm5220 preliminary data sheet 04/20/04 section 5: register summary .......................................................................................... 18 media independent interface (mii) management interface: register programming .............................18 preamble (pre) ................................................................................................................. ............18 start of frame (st) ............................................................................................................ ............18 operation code (op) ............................................................................................................ .........18 phy address (phyad) ............................................................................................................ ......18 register address (regad)....................................................................................................... .....18 turnaround (ta)................................................................................................................ .............19 data........................................................................................................................... .....................19 idle........................................................................................................................... .......................19 reset .......................................................................................................................... ....................24 loopback....................................................................................................................... .................24 forced speed selection ......................................................................................................... ........24 auto-negotiation enable ........................................................................................................ ........25 power down ..................................................................................................................... ..............25 isolate........................................................................................................................ .....................25 restart auto-negotiation ....................................................................................................... .........25 duplex mode .................................................................................................................... ..............25 collision test................................................................................................................. .................25 reserved bits .................................................................................................................. ...............25 mii status register ............................................................................................................................... ......26 100base-t4 capability.......................................................................................................... ........26 100base-x full-duplex capability ............................................................................................... .26 100base-x half-duplex capability............................................................................................... .26 10base-t full-duplex capability ................................................................................................ ..26 10base-t half-duplex capability................................................................................................ ..27 reserved bits .................................................................................................................. ...............27 preamble suppression ........................................................................................................... ........27 auto-negotiation complete ...................................................................................................... ......27 remote fault................................................................................................................... ...............27 auto-negotiation capability.................................................................................................... ........27 link status.................................................................................................................... ..................27 jabber detect .................................................................................................................. ...............27 extended capability ............................................................................................................ ...........27
broadcom corporation document 5220-ds04-405-r page v preliminary data sheet bcm5220 04/20/04 next page ...................................................................................................................... ................ 29 reserved bits .................................................................................................................. .............. 29 remote fault ................................................................................................................... .............. 29 reserved technologies bits ..................................................................................................... ..... 29 pause.......................................................................................................................... ................... 29 advertisement bits ............................................................................................................. ............ 30 selector field ................................................................................................................. ................ 30 lp next page................................................................................................................... .............. 31 lp acknowledge ................................................................................................................. ........... 31 lp remote fault ................................................................................................................ ............ 31 reserved bits .................................................................................................................. .............. 31 lp advertise pause ............................................................................................................. .......... 31 lp advertise bits .............................................................................................................. ............. 32 lp selector field .............................................................................................................. ............. 32 reserved bits .................................................................................................................. .............. 33 parallel detection fault....................................................................................................... ........... 33 link partner next page able .................................................................................................... ..... 33 next page able ................................................................................................................. ............. 33 page received .................................................................................................................. ............ 33 link partner auto-negotiation able ............................................................................................. .. 34 next page ...................................................................................................................... ................ 35 message page ................................................................................................................... ............ 35 acknowledge 2 .................................................................................................................. ............ 35 toggle ......................................................................................................................... ................... 35 message code field ............................................................................................................. ......... 35 unformatted code field......................................................................................................... ........ 35 auto-negotiation link partner (lp) next page transmit register ........................................................ 36 next page ...................................................................................................................... ................ 36 message page ................................................................................................................... ............ 36 acknowledge 2 .................................................................................................................. ............ 36 toggle ......................................................................................................................... ................... 36 message code field ............................................................................................................. ......... 36 unformatted code field......................................................................................................... ........ 36 transmit disable ............................................................................................................... ............. 37 bypass 4b5b encoder/decoder .................................................................................................... 37
broadcom corporation page vi document 5220-ds04-405-r bcm5220 preliminary data sheet 04/20/04 bypass scrambler/descrambler................................................................................................... ..37 bypass nrzi encoder/decoder .................................................................................................... .38 bypass receive symbol alignment................................................................................................ 38 baseline wander correction disable ............................................................................................. 38 fef enable ..................................................................................................................... ...............38 reserved bits .................................................................................................................. ...............38 fx mode........................................................................................................................ .................39 locked......................................................................................................................... ...................39 current 100base-x link status .................................................................................................. ..39 remote fault................................................................................................................... ...............39 false carrier detected ......................................................................................................... ..........40 bad esd detected ............................................................................................................... ..........40 receive error detected ......................................................................................................... .........40 transmit error detected ........................................................................................................ .........40 lock error detected ............................................................................................................ ...........40 mlt3 code error detected ....................................................................................................... .....40 receive error counter [15:0]................................................................................................... .......41 false carrier sense counter [7:0].............................................................................................. ....42 100base-x disconnect counter ...............................................................................................................42 ptest register ............................................................................................................................... ...............42 auxiliary control/status register .............................................................................................................43 jabber disable ................................................................................................................. ..............43 link force..................................................................................................................... ..................43 hsq and lsq .................................................................................................................... ............43 edge rate ...................................................................................................................... ................44 auto-negotiation indication .................................................................................................... ........44 force100/10 indication......................................................................................................... ..........44 speed indication............................................................................................................... ..............44 full-duplex indication......................................................................................................... ............44 fdx led enable ................................................................................................................. ...........46 interrupt enable............................................................................................................... ...............46 fdx mask....................................................................................................................... ................46 spd mask ....................................................................................................................... ...............46 link mask ...................................................................................................................... .................46 interrupt mask ................................................................................................................. ...............47
broadcom corporation document 5220-ds04-405-r page vii preliminary data sheet bcm5220 04/20/04 fdx change ..................................................................................................................... ............. 47 spd change ..................................................................................................................... ............. 47 link change.................................................................................................................... ............... 47 interrupt status ............................................................................................................... ............... 47 auxiliary mode 2 register ......................................................................................................................... 47 10base-t dribble bit correct ................................................................................................... .... 47 token ring mode ................................................................................................................ .......... 48 block 10base-t echo mode ....................................................................................................... .. 48 traffic meter led mode......................................................................................................... ........ 48 activity led force on .......................................................................................................... ......... 48 activity/link led mode ......................................................................................................... ......... 48 qualified parallel detect mode ................................................................................................. ..... 48 manchester code error .......................................................................................................... ....... 49 end of frame error ............................................................................................................. ........... 49 auto-negotiation indication.................................................................................................... ........ 49 force 100/10 indication ........................................................................................................ ......... 49 speed indication ............................................................................................................... ............. 50 full-duplex indication ......................................................................................................... ........... 50 auxiliary mode register ............................................................................................................................ 50 activity led disable ........................................................................................................... ........... 50 link led disable ............................................................................................................... ............ 50 block txen mode ................................................................................................................ ......... 51 auxiliary multiple phy register ................................................................................................................ 51 hcd bits ....................................................................................................................... ................. 51 restart auto-negotiation ....................................................................................................... ........ 52 auto-negotiation complete...................................................................................................... ...... 52 acknowledge complete ........................................................................................................... ...... 52 acknowledge detected ........................................................................................................... ....... 52 ability detect ................................................................................................................. ................. 52 super isolate.................................................................................................................. ................ 52 10base-t serial mode........................................................................................................... ....... 52 shadow register enable ......................................................................................................... ...... 53 force led [1:0]................................................................................................................ .............. 54 enable clock during low power .................................................................................................. .54 force iddq mode................................................................................................................ .......... 54
broadcom corporation page viii document 5220-ds04-405-r bcm5220 preliminary data sheet 04/20/04 mlt3 detected.................................................................................................................. .............55 apd enable..................................................................................................................... ...............55 apd sleep timer ................................................................................................................ ...........55 apd wake-up timer [3:0] ........................................................................................................ ......55 auxiliary status 3 register (shadow register) ........................................................................................56 noise [7:0] .................................................................................................................... ..................56 fifo consumption [3:0] ......................................................................................................... ........56 auxiliary mode 3 register (shadow register) .........................................................................................56 fifo size select [3:0] ......................................................................................................... ...........57 auxiliary status 4 register (shadow register) ........................................................................................57 packet length counter [15:0]................................................................................................... ......57 section 6: timing and ac characteristics ...................................................................... 58 section 7: electrical characteristics ............................................................................... 71 section 8: application example ....................................................................................... 73 section 9: thermal characteristics ................................................................................. 74 section 10: mechanical information ................................................................................ 75 section 11: ordering information .................................................................................... 77
broadcom corporation document 5220-ds04-405-r page ix preliminary data sheet bcm5220 04/20/04 l ist of t ables table 1: 4b5b encoding......................................................................................................... ............................ 5 table 2: receive error encoding................................................................................................ ........................ 6 table 3: pin descriptions...................................................................................................... .............................. 7 table 4: 10base-t serial mode (7-wire) signals................................................................................. ........... 15 table 5: low power modes ....................................................................................................... ....................... 17 table 6: mii management frame format........................................................................................... .............. 18 table 7: mii register map summary.............................................................................................. .................. 21 table 8: mii shadow register map summary....................................................................................... ........... 23 table 9: mii control register (address 00000b, 0d, 00h) ....................................................................... ........ 24 table 10: mii status register (address 00001b, 01d, 01h) ....................................................................... ...... 26 table 11: phy identifier registers (addresses 00010 and 00011b, 02 and 03b, 02 and 03h) ........................ 28 table 12: auto-negotiation advertisement register (address 04d, 04h)......................................................... 29 table 13: auto-negotiation link partner ability register (address 05d, 05h) .................................................. 31 table 14: auto-negotiation expansion register (address 00110b, 6d, 06h) ................................................... 33 table 15: next page transmit register (address 07d, 07h)....................................................................... ..... 35 table 16: next page transmit register (address 08d, 08h)....................................................................... ..... 36 table 17: 100base-x auxiliary control register (address 16d, 10h) ............................................................. 3 7 table 18: 100base-x auxiliary status register (address 17d, 11h)............................................................... 39 table 19: 100base-x receive error counter (address 18d, 12h) .................................................................. 4 1 table 20: 100base-x false carrier sense counter (address 19d, 13h) ........................................................ 42 table 21: 100base-x disconnect counter (address 20d, 14h) ...................................................................... 42 table 22: ptest register (address 10111b, 23d, 17h) ............................................................................ ...... 42 table 23: auxiliary control/status register (address 24d, 18h) ................................................................. ..... 43 table 24: auxiliary status summary register (address 25d, 19h) ................................................................. .45 table 25: interrupt register (address 26d, 1ah)................................................................................ .............. 46 table 26: auxiliary mode 2 register (address 27d, 1bh)......................................................................... ........ 47 table 27: 10base-t auxiliary error & general status register (address 28d, 1ch) ...................................... 49 table 28: auxiliary mode register (address 29d, 1dh) ........................................................................... ........ 50 table 29: auxiliary multiple phy register (address 30d, 1eh)................................................................... ..... 51 table 30: broadcom test (address 31d, 1fh) ..................................................................................... ............ 53 table 31: auxiliary mode 4 register (shadow register 26d, 1ah) ................................................................. .54 table 32: auxiliary status 2 register (shadow register 27d, 1bh) ............................................................... .. 55
broadcom corporation page x document 5220-ds04-405-r bcm5220 preliminary data sheet 04/20/04 table 33: auxiliary status 3 register (shadow register 28d, 1ch)............................................................... ...56 table 34: auxiliary mode 3 register (shadow register 29d, 1dh)................................................................. ..56 table 35: current receive fifo size ............................................................................................ ...................57 table 36: auxiliary status 4 register (shadow register 30d, 1eh)............................................................... ...57 table 37: clock timing ......................................................................................................... ............................58 table 38: reset timing ......................................................................................................... ............................58 table 39: mii 100base-x transmit timing ........................................................................................ ..............59 table 40: mii 100base-x receive timing ......................................................................................... ..............61 table 41: mii 10base-t transmit timing ......................................................................................... ...............63 table 42: mii 10base-t receive timing .......................................................................................... ...............64 table 43: mii 10base-t collision timing........................................................................................ .................65 table 44: 10base-t serial transmit timing ...................................................................................... ..............65 table 45: 10base-t serial receive timing ....................................................................................... ..............66 table 46: loopback timing (mii) ................................................................................................ ......................67 table 47: auto-negotiation timing .............................................................................................. .....................67 table 48: led timing ........................................................................................................... ............................67 table 49: management data interface timing..................................................................................... .............68 table 50: rmii transmit timing................................................................................................. .......................69 table 51: rmii receive timing.................................................................................................. .......................69 table 52: rmii 100base-x propagation delay timing .............................................................................. ......70 table 53: rmii 10base-t propagation delay timing ............................................................................... .......70 table 54: absolute maximum ratings ............................................................................................. .................71 table 55: recommended operating conditions for bcm5220......................................................................... 71 table 56: electrical characteristics........................................................................................... ........................71 table 57: theta-ja vs. airflow for the bcm5220kpb (fbga 64).................................................................... .74 table 58: theta-ja vs. airflow for the BCM5220KPT (64 tqfp) .................................................................... .74
broadcom corporation document 5220-ds04-405-r page xi preliminary data sheet bcm5220 04/20/04 l ist of f igures figure 1: functional block diagram ............................................................................................. ........................i figure 1: bcm5220kpb ballout diagram........................................................................................... .............. 11 figure 2: BCM5220KPT pin diagram............................................................................................... ................ 12 figure 3: clock and reset timing ............................................................................................... ..................... 59 figure 4: mii transmit start of packet timing (100base-tx) ..................................................................... .... 60 figure 5: mii transmit end of packet timing (100base-tx) ....................................................................... ... 60 figure 6: mii receive start of packet timing (100base-tx) ...................................................................... .... 61 figure 7: mii receive end of packet timing (100base-tx) ........................................................................ ... 62 figure 8: mii receive packet premature end (100base-tx) ........................................................................ .62 figure 9: mii link failure or stream cipher error during receive packet ....................................................... 6 3 figure 10: mii false carrier sense timing (100base-tx)......................................................................... ..... 63 figure 11: mii 10base-t transmit start of packet timing ........................................................................ ...... 64 figure 12: 10base-t serial transmit timing ..................................................................................... ............. 66 figure 13: 10base-t serial receive timing ...................................................................................... ............. 67 figure 14: management interface timing......................................................................................... ................ 68 figure 15: management interface timing (with preamble suppression on).................................................... 68 figure 16: rmii transmit packet timing ......................................................................................... ................. 69 figure 17: rmii receive packet timing .......................................................................................... ................. 70 figure 18: power connections bcm5220 (3.3v) .................................................................................... ......... 73 figure 19: 64-pin tqfp 10mm package (bcm5220 kpt) .............................................................................. 75 figure 20: fbga 64-pin package, 8 mm x 8 mm (bcm5220 kpb) ................................................................. 76
broadcom corporation page xii document 5220-ds04-405-r bcm5220 preliminary data sheet 04/20/04
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r overview page 1 section 1: functional description o verview the bcm5220 is a single-chip fast ethernet transceiver. it performs all of the physical layer interface functions for 100base- tx full-or half-duplex ethernet on cat 5 twisted pair cable and 10base-t full-or half-duplex ethernet on cat 3, 4 or 5 cable. it may also be configured for 100base-fx full-or half-duplex transmission over fiber-optic cabling when paired with an external fiber-optic line driver and receiver. the chip performs 4b5b, mlt3, nrzi, and manchester enco ding and decoding, clock and data recovery, stream cipher scrambling/descrambling, digital adaptive equalization, line transmission, carrier sense and link integrity monitor, auto- negotiation and media independent interface (mii) managem ent functions. the bcm5220 can be connected to a mac switch controller through the mii on one side, and connects directly to the network media on the other side (through isolation transformers for unshielded twisted pair (utp) modes or fi ber-optic transmitter/receiver components for fx modes). the bcm5220 is fully compliant with the ieee 802.3 and 802.3u standards. e ncoder /d ecoder in 100base-tx and 100base-fx modes, the bcm5220 transmits and receives a continuous data stream on twisted-pair or fiber-optic cable. when the mii transmit enable is asserted, nibble-wide (4-bit) data from the transmit data pins is encoded into 5-bit code groups and inserted into the transmit data stream. the 4b5b encoding is shown in table 1 on page 5. the transmit packet is encapsulated by replacing the first 2 nibbles of preamble with a start of stream delimiter (j/k codes) and appending an end of stream delimiter (t/r codes) to the end of the packet. when the mii transmit error input is asserted during a packet, the transmit error code group (h) is sent in place of the corresponding data code group. the transmitter repeatedly sends the idle code group between packets. in tx mode, the encoded data stream is scrambled by a stream cipher block and then serialized and encoded into mlt3 signal levels. a multi-mode transmit dac is used to drive the mlt3 data onto the twisted pair cable. in fx mode, the scrambling function is bypassed and the data is nrzi encoded. the multimode transmit dac drives differential positive ecl (pecl) levels to an external fiber-optic transmitter. following baseline wander correction, adaptive equalization, an d clock recovery in tx mode, the receive data stream is converted from mlt3 to serial nrz data. the nrz data is descrambled by the stream cipher block and then deserialized and aligned into 5-bit code groups. in fx mode, the receive data stream differential pecl levels are sampled from the fiber-optic receiver. baseline wander correction, adaptive equalization, and stream cipher descrambling functions are bypassed and nrzi decoding is used instead of mlt3. the 5-bit code groups are decoded into 4-bit data nibbles, as shown in table 1. the start of stream delimiter is replaced with preamble nibbles and the end of stream delimiter and idle codes are replaced with all zeros. the decoded data is driven onto the mii receive data pins. when an invalid code group is detected in the data stream, the bcm5220 asserts the mii rxer signal. the chip also asserts rxer for several other error conditions that improperly terminate the data stream. while rxer is asserted, the receive data pins are driven with a 4-bit code indicating the type of error detected. the error codes are list ed in table 2 on page 6.
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 2 link monitor document 5220-ds04-405-r in 10base-t mode, manchester encoding and decoding is pe rformed on the data stream. the multimode transmit dac performs pre-equalization for 100 meters of cat 3 cable. l ink m onitor in 100base-tx mode, receive signal energy is detected by monitoring the receive pair for transitions in the signal level. signal levels are qualified using squelch detect circuits. when no signal or certain invalid signals are detected on the receiv e pair, the link monitor enters and remains in the link fail state, where only idle codes are transmitted. when a valid signal is detected on the receive pair for a minimum period of time, the link monitor enters the link pass state and the transmit and receive functions are enabled. in 100base-fx mode, the external fiber-optic receiver performs the signal energy detection function and communicates this information directly to the bcm5220 through the differential sd pins. in 10base-t mode, a link-pulse detection circuit constantly monitors the rd pins for the presence of valid link pulses. c arrier s ense in 100base-x modes, carrier sense is asserted asynchronously on the crs pin as soon as activity is detected in the receive data stream. rxdv is asserted as soon as a valid start-of-stream delimiter (ssd) is detected. carrier sense and rxdv are deasserted synchronously upon detection of a valid end of stream delimiter or two consecutive idle code groups in the receive data stream. if carrier sense is asserted and a valid ssd is not detected immediately, then rxer is asserted in place of rxdv. a value of 1110 is driven on the receive data pins to indicate false carrier sense. in 10base-t mode, carrier sense is asserted asynchronously on the crs pin when valid preamble activity is detected on the rd+/ ? input pins. in half-duplex dte mode, the bcm5220 asserts carrier sense while transmit enable is asserted and the link monitor is in the pass state. in full-duplex mode, crs is only asserted for receive activity. c ollision d etection in half-duplex mode, collision detect is asserted on the col pin whenever carrier sense is asserted and transmission is in progress.
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r digital adaptive equalizer page 3 a uto -n egotiation the bcm5220 contains the ability to negotiate its mode of operation over the twisted pair link using the auto-negotiation mechanism defined in the ieee 802.3u specification. auto-negotiation can be enabled or disabled by hardware or software control. when the auto-negotiation function is enabled, the bcm5220 automatically chooses its mode of operation by advertising its abilities and comparing them with those received from its link partner. the bcm5220 can be configured to advertise 100base-tx fu ll-duplex and/or half-duplex and 10base-t full-and/or half- duplex. the transceiver negotiates with its link partner and chooses the highest level of operation available for its own link. auto-negotiation is not operational during 100base-fx operation. d igital a daptive e qualizer the digital adaptive equalizer removes intersymbol interference (isi) created by the transmission channel media. the equalizer accepts sampled unequalized data from the adc on each channel and produces equalized data. the bcm5220 achieves an optimum signal-to-noise ratio by using a combination of feed forward equalization and decision feedback equalization. this powerful technique achieves a 100base-tx ber of less than 1 x 10 -12 for transmission up to 100 meters on cat 5 twisted pair cable, even in harsh noise environments. the digital adaptive equalizers in the bcm5220 achieve performance close to theoretical limits. the all-digital nature of the design makes the performance very tolerant to on-chip noise. the filter coefficients are self-adapting to any quality of cable or cable length. due to transmit pre-equalization in 10base-t mode and complete lack of isi in 100base-fx mode, the adaptive equalizer is bypassed in these two modes of operation. adc the receive channel has a 6-bit, 125-mhz analog-to-digital converter (adc). the adc samples the incoming data on the receive channel and produces a 6-bit output. the output of the adc is fed to the digital adaptive equalizer. advanced analog circuit techniques achieve low-offset, high-power-supply noise rejection, fast settling time, and low bit error rate. d igital c lock r ecovery /g enerator the all-digital clock recovery and generator block creates all internal transmit and receive clocks. the transmit clock is lock ed to the 25-mhz clock input, while the receive clock is locked to the incoming data stream. clock recovery circuits optimized to mlt3, nrzi, and manchester encoding schemes are included for use with each of the three different operating modes. the input data stream is sampled by the recovered clock and fed synchronously to the digital adaptive equalizer.
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 4 multimode transmit dac document 5220-ds04-405-r b aseline w ander c orrection a 100base-tx data stream is not always dc balanced. because the receive signal must pass through a transformer, the dc offset of the differential receive input can wander. this effect, known as baseline wander, can greatly reduce the noise immunity of the receiver. the bcm5220 automatically compensates for baseline wander by removing the dc offset from the input signal, and thereby significantly reduces the chance of a receive symbol error. the baseline wander correction circuit is not required, and therefore is bypassed, in 10base-t and 100base-fx operating modes. m ultimode t ransmit dac the multimode transmit digital-to-analog converter (dac) transmits mlt3-coded symbols in 100base-tx mode, nrzi- coded symbols in 100base-fx mode, and manchester-coded symbols in 10base-t mode. it allows programmable edge- rate control in tx mode, which decreases unwanted high frequency signal components, thus reducing emi. high-frequency pre-emphasis is performed in 10base-t mode; no filtering is performed in 100base-fx mode. the transmit dac utilizes a current drive output, which is well balanced and produces very low noise transmit signals. pecl voltage levels are produced with resistive terminations in 100base-fx mode. s tream c ipher in 100base-tx mode, the transmit data stream is scrambled to reduce radiated emissions on the twisted-pair cable. the data is scrambled by exclusive oring the nrz signal with the output of an 11-bit-wide linear feedback shift register (lfsr), which produces a 2047-bit non-repeating sequence. the scrambler reduces peak emissions by randomly spreading the signal energy over the transmit frequency range and eliminating peaks at certain frequencies. the receiver descrambles the incoming data stream by ex clusive oring it with the same sequence generated at the transmitter. the descrambler detects the state of the transmit lfsr by looking for a sequence representing consecutive idle codes. the descrambler locks to the scrambler state after detecting a sufficient number of consecutive idle code-groups. the receiver does not attempt to decode the data stream unless the descrambler is locked. when locked, the descrambler continuously monitors the data stream to make sure that it has not lost synchronization. the receive data stream is expected to contain inter-packet idle periods. if the descrambler does not detect enough idle codes within 724 s, it becomes unlocked, and the receive decoder is disabled. the descrambler is always forced into the unlocked state when a link failure condition is detected. a special node called high speed token ring can be enabled. it increases the scrambler timeout from 724 s to 5816 s, thus allowing frames as large as the token ring maximum length to be received without error. stream cipher scrambling/descrambling is not used in 100base-fx and 10base-t modes.
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r far-end fault page 5 f ar -e nd f ault auto-negotiation provides a remote fault capability for detection of asymmetric link failures. since auto-negotiation is not available for 100base-fx, the bcm5220 implements the ieee 802.3 standard far-end fault mechanism for the indication and detection of remote error conditions. when the far-end fault mechanism is enabled, a transceiver transmits the far- end fault indication whenever a receive channel failure is detected (signal detect is deasserted). the transceiver also continuously monitors the receive channel when a valid signal is present (signal detect asserted). when its link partner is indicating a remote error, the transceiver forces its link monitor into the link fail state and sets the remote fault bit in th e mii status register. the far-end fault mechanism is enabled by default in 100base-fx mode and disabled in 100base-tx and 10base-t modes, and can be controlled by software after reset. mii m anagement the bcm5220 contains a complete set of mii management registers accessible by using the management clock line (mdc) and the bidirectional serial data line (mdio). many transceivers can be bussed together on a single mdio/mdc wire pair by giving each a unique phy address, defined by configuring the five external phy address input pins. every time an mii read or write operation is executed, the bcm5220 compares the operation?s phy address with its own phy address definition. the operation is executed only when the addresses match. for further details, see section 5: ?register summary? on page 18. table 1: 4b5b encoding name 4b code 5b code meaning 0 0000 11110 data 0 1 0001 01001 data 1 2 0010 10100 data 2 3 0011 10101 data 3 4 0100 01010 data 4 5 0101 01011 data 5 6 0110 01110 data 6 7 0111 01111 data 7 8 1000 10010 data 8 9 1001 10011 data 9 a 1010 10110 data a b 1011 10111 data b c 1100 11010 data c d 1101 11011 data d e 1110 11100 data e f 1111 11101 data f i 0000* 11111 idle j 0101* 11000 start-of-stream delimiter, part 1
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 6 mii management document 5220-ds04-405-r k 0101* 10001 start-of-stream delimiter, part 2 t 0000* 01101 end-of-stream delimiter, part 1 r 0000* 00111 end-of-stream delimiter, part 2 h 1000 00100 transmit error (used to force signalling errors) v 0111 00000 invalid code v 0111 00001 invalid code v 0111 00010 invalid code v 0111 00011 invalid code v 0111 00101 invalid code v 0111 00110 invalid code v 0111 01000 invalid code v 0111 011000 invalid code v 0111 10000 invalid code v 0111 11001 invalid code * treated as invalid code (mapped to 0111) when received in data field. table 2: receive error encoding error type rxd[3:0] stream cipher error?descrambler lost lock 0010 link failure 0011 premature end of stream 0110 invalid code 0111 transmit error 1000 false carrier sense 1110 table 1: 4b5b encoding (cont.) name 4b code 5b code meaning
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r mii management page 7 section 2: hardware signal definition table table 3 provides the pin descriptions for the bcm5220. table 3: pin descriptions 5220kpb 5220kpt pin label type description media connections h4 g4 26 25 rd+ rd ? i receive pair. differential data from the media is received on the rd signal pair. h5 g5 31 30 td+ td ? o transmit pair. differential data is transmitted to the media on the td signal pair. clock d1 c1 6 5 xtali xtalo i o crystal input, output for mii mode only. if these pins are used, then ref_clk must be left open. a 25-mhz, parallel-resonant crystal can be connected between these pins. accuracy of the crystal is 50 ppm. connect an appropriate value capacitor from each pin to gnd. whenever ref_clk pin is used, ground xtali pin and leave xtalo pin unconnected. b1 4 ref_clk i pd mii 25-mhz reference clock input. whenever ref_clk pin is used, ground xtali pin and leave xtalo pin unconnected. this pin must be driven with a continuous 25-mhz clock. accuracy is +/-50 ppm, with a duty cycle between 35% and 65% inclusive. this pin must be left unconnected when using pins xtali and xtalo. mii interface b6 53 txc o 3s transmit clock. 25-mhz output in 100base-x mode and 2.5 mhz in 10base-t mii mode. 10-mhz output in 10base-t serial mode. this clock is a continuously driven output, generated from the xtali input. b4 b5 a4 a5 60 59 58 57 txd3 txd2 txd1 txd0 i pd mii transmit data input. nibble-wide transmit data stream is input on these pins synchronous with txc. txd[3] is the most significant bit. only txd0 is used in 10base-t serial mode. a6 56 txen i pd mii transmit enable. active high. indicates that the data nibble on txd[3:0] is valid. a7 52 txer i pd mii transmit error. an active high input is asserted when a transmit error condition is requested by the mac. b7 50 rxc o 3s mii receive clock. 25-mhz output in 100base-x mii mode and 2.5-mhz output in 10base-t mode. 10-mhz output in 10base- t serial mode. this clock is recovered from the incoming data on the cable inputs. rxc is a continuously running output clock resynchronized at the start of each incoming packet. this synchronization may result in an elongated period during one cycle while rxdv is low. e8 d8 c8 b8 43 44 47 48 rxd3 rxd2 rxd1 rxd0 o 3s mii receive data outputs. nibble-wide receive data stream is driven out on these pins synchronous with rxc. rxd[3] is the most significant bit. only rxd0 is used in 10base-t serial mode. [msb:lsb]; # = active-low signal, i = input, o = output, i/o = bidirectional, i pu = input w/ internal pull-up, o od = open-drain output, o 3s = three-state output, b = bias, pwr = power supply, gnd = ground
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 8 mii management document 5220-ds04-405-r c6 49 rxdv o 3s mii receive data valid. active high. indicates that a receive frame is in progress, and that the data stream present on the rxd output pins is valid. a8 51 rxer o 3s mii receive error detected. active high. indicates that an error is occurring during a receive frame. a3 62 crs/ crs_dv o 3s mii carrier sense. active high. indicates traffic on link. in 100base-x modes, crs is asserted when a non-idle condition is detected in the receive data stream and deasserted when idle or a valid end of stream delimiter is detected. in 10base-t mode, crs is asserted when a valid preamble is detected and deasserted when end-of-file or an idle condition is detected. crs is also asserted during transmission of packets except in full- duplex modes. crs is an asynchronous output signal. b3 61 col o 3s collision detect. in half-duplex modes, active high output indicates that a collision has occurred. in full-duplex mode, col remains low. col is an asynchronous output signal. e6 41 mdio i/o pu management data i/o. this serial input/output bit is used to read from and write to the mii registers. the data value on the mdio pin is valid and latched on the rising edge of mdc. d7 42 mdc i pd management data clock. the mdc clock input must be provided to allow mii management functions. clock frequencies up to 12.5 mhz are supported. mode d2 9 reset# i pu reset. active low. resets the bcm5220. also used to enable power off and low power modes. e3 e2 d3 d5 c4 14 13 12 11 10 phyad4 phyad3/pause phyad2/ act_led# phyad1/ col_led# phyad0/ fdx_led# i/o pd phy address selects phyad[4:0]. these inputs set the mii management phy address. these pins are sampled only during power-on reset. during normal operation these pins become outputs. pause. status of the link partner?s pause bit, bit 10d of mii link partner ability register 05d. activity led. active low. the activity led is driven low for approximately 80 ms each time there is receive or transmit activity while in the link pass state. collision detect led. active low. this is a stretched col signal (pin 61) that is suitable for led display. full-duplex led. the full-duplex led is driven low when operating in full-duplex mode and driven high in half-duplex mode. f8 39 fdx i pd full-duplex mode. when auto-negotiation is disabled, the fdx pin is logically ored with register 00, bit 8 to select full-duplex (1) or half-duplex (0) operation. table 3: pin descriptions (cont.) 5220kpb 5220kpt pin label type description [msb:lsb]; # = active-low signal, i = input, o = output, i/o = bidirectional, i pu = input w/ internal pull-up, o od = open-drain output, o 3s = three-state output, b = bias, pwr = power supply, gnd = ground
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r mii management page 9 f6 37 f100 tck i pu force 100base-x control. when 100base-fx mode is not selected, the f100 function is enabled. when f100 is high and anen is low, the transceiver is forced to 100base-tx operation. when f100 is low and anen is low, the transceiver is forced to 10base-t operation. when anen is high, f100 has no effect on operation. test clock. this pin becomes tck if jtag_en pin is high. clock input used to synchronize jtag tap control and data transfers. f7 38 anen trst# i pu auto-negotiation enable. when 100base-fx is not selected, the anen function is enabled. anen is active high. when pulled high, auto-negotiation begins immediately after reset. when low, auto-negotiation is disabled by default. test reset. this pin becomes trst# if jtag_en pin is high. asynchronous active low reset input to the jtag tap controller. must be set low to ensure the tap controller initializes to the test-logic-reset state. g2 g1 21 19 sd+ sd- i pd 100base-fx signal detect. 100base-fx mode is selected if sd+/- pins are presented with a valid pecl differential signal. leaving this pin unconnected or connecting them to ground causes the bcm5220 to operate in tx mode. when 100base- fx is selected, sd+ and sd ? indicate signal quality status on the fiber optic link. when the signal quality is good, the sd+ pin will be high relative to the sd ? pin. e4 15 testen i pd test mode enable. active high. can float or be grounded for normal operation. f1 16 low_pwr i pd low power mode enable. active high input places the bcm5220 into low power operation with the chip deactivated except for the energy detect block and the crystal oscillator. when asserted with reset# pulled low, the entire chip is deactivated (power off mode). f2 17 energy_det o 3s energy detection. active high output indicates the presence of a signal on rd+/ ? receive analog wire pair. operational in all modes of operation except iddq. bias h3 23 rdac b dac bias resistor. adjusts the current level of the transmit dac. a resistor of 1.27 k ? 1% must be connected between the rdac pin and gnd. leds h8 35 lnkled# tdi i/o pu link integrity led. the link integrity led indicates the link status of the phy. lnkled# is driven low when the link to the phy is good. when bit 12 of register 1dh is set to 1, lnkled# is driven low when the 100base-tx link is good. test data input. this pin becomes tdi if jtag_en is high. serial data input to the jtag tap controller. this pin is sampled on the rising edge of tck. table 3: pin descriptions (cont.) 5220kpb 5220kpt pin label type description [msb:lsb]; # = active-low signal, i = input, o = output, i/o = bidirectional, i pu = input w/ internal pull-up, o od = open-drain output, o 3s = three-state output, b = bias, pwr = power supply, gnd = ground
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 10 mii management document 5220-ds04-405-r g8 36 spdled# adv_pause# tms i/o pu 100base-x led. the 100base-x led is driven low when operating in 100base-x modes and high when operating in 10base-t modes. when bit 12 of register 1dh is set to 1, spdled# is driven low when the 100base-t link is good. adv_pause#. active low. during power-on reset, this pin is sampled and causes the default value of mii auto-negotiation advertisement register, 4, bit 10d to be set accordingly. test mode select. this pin becomes tms if jtag_en is high. single control input to the jtag tap controller is used to traverse the test-logic state machine. sampled on the rising edge of tck. g7 34 xmtled# intr# fdxled# o od transmit activity led. active low output. the transmit activity led is driven low for approximately 80 ms each time there is transmit activity while in the link pass state. when the interrupt mode is enabled, pin becomes intr#. when fdxled mode is enabled, pin becomes fdxled#. h7 33 rcvled# actled# tdo i/o pu receive activity led. active low output. the receive activity led is driven low for approximately 80 ms each time there is receive activity while in the link pass state. in either interrupt or fdxled mode, pin becomes actled#, indicating both receive and transmit activity. test data output. this pin becomes tdo if jtag_en is high. serial data output from the jtag tap controller. updated on the falling edge of tck. jtag a2 64 jtag_en i pd jtag enable. active high. when high causes the bcm5220 to enter jtag test mode. for normal operation leave this pin unconnected. power a1 3 regdvdd pwr digital voltage regulator input. connect this pin to a digital 3.3v supply. h1 20 regavdd pwr analog voltage regulator input. connect this pin to an analog 3.3v supply. c3, c5 2, 55 dvdd pwr digital regulator output (2.5v). connect these pins to decoupling capacitors as shown in figure 18 on page 73. f4, f5 27, 28 avdd pwr analog regulator output vdd (2.5v). connect these pins to decoupling capacitors as shown in figure 18 on page 73. b2, e7, f3 1, 46, 18 ovdd pwr 3.3v digital periphery (output buffer) vdd supply. c7, d4, d6, e5 40, 45 54, 63 dgnd gnd digital ground. g6, h6 29, 32 agnd gnd analog ground. e1 7 xtalgnd gnd crystal ground. h2 22 biasvdd pwr bias vdd. connect this pin to avdd. g3 24 biasgnd gnd bias ground. connect this pin to agnd. c2 8 ovdd/nc pwr this pin is for factory test only. for normal operation, leave this pin unconnected or connect to ovdd supply table 3: pin descriptions (cont.) 5220kpb 5220kpt pin label type description [msb:lsb]; # = active-low signal, i = input, o = output, i/o = bidirectional, i pu = input w/ internal pull-up, o od = open-drain output, o 3s = three-state output, b = bias, pwr = power supply, gnd = ground
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r mii management page 11 section 3: pinout diagram figure 1 below provides the pinout diagram for the bcm5220kpb package. figure 1: bcm5220kpb ballout diagram regdvdd jtag_en crs/ crs_dv txd1 txd0 txen txer rxer ref_clk ovdd col txd3 txd2 txc rxc rxd0 xtalo ovdd/nc dvdd phyad0 fdx_led# dvdd rxdv dgnd rxd1 xtali reset# phyad2 act_led# dgnd phyad1 col_led# dgnd mdc rxd2 xtalgnd phyad3 pause phyad4 ck25 testen dgnd mdio ovdd rxd3 low_pwr energy_d et ovdd avdd avdd f100 tck anen trst# fdx sd- sd+ biasgnd rd- td- agnd xmtled# intr# fdxled# spdled# adv_ pause# tms regavdd biasvdd rdac rd+ td+ agnd rcvled# actled# tdo lnkled# tdi b a c d e f g h 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 b a c d e f g h
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 12 mii management document 5220-ds04-405-r figure 2 below provides the pin diagram for the BCM5220KPT. figure 2: BCM5220KPT pin diagram sd- regavdd sd+ biasvdd rd + td + biasgnd rd - rdac td - avdd agnd avdd txd1 txd0 rxdv rxc txd2 agnd anen/trst# rxd3 mdc f100/tck txd3 dgnd crs/crs_d v jtag_en col txer rxer txc dgnd txen dvdd rxd0 rxd1 phyad4/ck25 reset# ovdd/nc testen ovdd dvdd regdvdd ref_clk xtali xtalgnd low_pwr phyad3/pause p hyad1/col_led# phyad2/act_led# phyad0/fdx_led# ovdd ognd rxd2 ognd energy_det ovdd rcvled#/actled#/tdo spdled#/adv_pause#/tms xmtled#/intr#/fdxled# lnkled#/tdi mdio fdx bcm5220 kpt 46 47 48 45 38 34 44 36 42 43 35 37 40 39 33 41 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 23 26 25 28 27 30 29 32 31 62 64 60 61 58 59 56 57 54 55 63 53 51 52 49 50 (top view) xtalo
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r reset page 13 section 4: operational description r eset there are two ways to reset the bcm5220. a hardware reset pin is provided that resets all internal nodes in the chip to a known state. reset# pin must be held low when powering the bcm5220 to get this chip into normal mode. if the bcm5220 is not provided a power-on reset, it is possible for the chip to power up in a low power mode. to exit this low power mode, reset# pin must be held low for at least 20 s. hardware reset should always be applied to the bcm5220 after power-up. the bcm5220 also has a software reset capability. to perform software reset, a 1 must be written to bit 15 of the mii control register. this bit is self-clearing, meaning that a second write operation is not necessary to end the reset. there is no effec t if a 0 is written to the mii control register reset bit . the bcm5220 clock input can be driven two ways: internal crystal oscillator or external oscillator. to take advantage of the internal oscillator, attach a 25-mhz crystal between the xtali and xtalo pins. connect 27 pf capacitors from each pin to ground. alternatively, a 50% duty cycle 25-mhz clock can be directly applied to the xtali pin. in this case, the xtalo output must be left unconnected. no capacitors are used. i solate m ode when the bcm5220 is put into isolate mode, all mii inputs (txd[3:0], txen, and txer) are ignored, and all mii outputs (txc, col, crs, rxc, rxdv, rxer, and rxd[3:0]) are set to high impedance. only the mii management pins (mdc, mdio) operate normally. upon resetting the chip, the isolate mode is off. writing a 1 to bit 10 of the mii control register put s the transceiver into isolate mode. writing a 0 to the same bit removes it from isolate mode. l oopback m ode loopback mode allows in-circuit testing of the bcm5220 chip . all packets sent in through the txd pins are looped-back internally to the rxd pins, and are not sent out to the cable. the loopback mode is enabled by writing a 1 to bit 14 of the mii control register. to resume normal operation, bit 14 of the mii control register must be 0. incoming packets on the cable are ignored in loopback mode. because of this, the col pin is normally not activated during loopback mode. to test that the col pin is actually working, the bcm5220 can be placed into collision test mode. this mode is enabled by writing a 1 to bit 7 of the mii control register. asserting txen causes the col output to go high, and deasserting txen causes the col output to go low. while in loopback mode, several function bypass modes are also available that can provide a number of different combinations of feedback paths during loopback testing. these bypass modes include bypass scrambler, bypass mlt3 encoder and bypass 4b5b encoder. all bypass modes can be accessed by writing bits of the auxiliary control register (10h).
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 14 full-duplex mode document 5220-ds04-405-r f ull -d uplex m ode the bcm5220 supports full-duplex operation. while in fu ll-duplex mode, a transceiver can simultaneously transmit and receive packets on the cable. the col signal is never activated when in full-duplex mode. the crs output is asserted only during receive packets, not transmit packets. by default, the bcm5220 powers up in half-duplex mode. when auto-negotiation is disabled, full-duplex operation can be enabled either by fdx pin control or by an mii register bit (register 0, bit 8). when auto-negotiation is enabled in dte mode, full-duplex capability is advertised by default, but can be overridden by a write to the auto-negotiation advertisement register (04h). one of the led outputs can be modified to signal full-duplex versus half-duplex operation. this capability is enabled by setting mii register 1ah, bit 15. in this mode, xmtled# becomes fdxled#, where a 1 output indicates half-duplex and a 0 output indicates full-duplex. this value is the inverse of mii register 18h, bit 0. when the fdxled mode is activated, the rcvled# becomes actled#. 100base-fx m ode for 100base-fx mode, the bcm5220 transceiver interfaces with an external 100base-fx fiber-optic driver and receiver instead of the magnetics module used with twisted-pair cable. the differential transmit and receive data pairs operate at pecl voltage levels instead of those required for twisted-pair transmission. the data stream is encoded using two-level nrzi instead of three-level mlt3. since scrambling is not used in 100base-fx operation, the stream cipher function is bypassed. the external fiber-optic receiver detects signal status and passes it into the bcm5220 through the sd pins. the sd pins select the 100base-fx mode. 10base-t m ode the same magnetics module used in 100base-tx mode can be used to interface to the twisted-pair cable when operating in 10base-t mode. the data is two-level manchester encoded instead of three-level mlt3, and no scrambling/ descrambling or 4b5b coding is performed. data and clock ra tes are decreased by a factor of 10, with the mii interface signals operating at 2.5 mhz. 10base-t s erial m ode the bcm5220 supports 10base-t serial mode, also known as the 7-wire interface. in this mode, 10base-t transmit and receive packets appear at the mii in serial fashion, at a rate of 10 mhz. receive packet data is output on rxd (0) synchronously with rxc. transmit packet data must be input on txd (0) synchronously with txc. both clocks toggle at 10 mhz.
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r special led modes page 15 the 10base-t serial mode is enabled by writing a 1 to bit 1 of the auxiliary multiple-phy register (1eh). this mode is not available in 100base-x modes. the following table shows the mii pins used in this mode and their direction of operation. s pecial led m odes traffic meter mode the blink rate of xmtled# and rcvled# is decreased dramatically to better show the volume of traffic. lower traffic levels make the corresponding led appear dimmer than higher traffic levels. this mode is activated by writing a 1 to bit 6 of the aux mode 2 register (1bh). force leds on the spdled#, lnkled#, xmtled#, rcvled#, col_led#, act_led#, and fdx_led# outputs can be forced on (0 value) by writing a 01 to bit 5 and 4 of shadow register 1ah. disable leds the spdled#, lnkled#, xmtled#, rcvled#, col_led#, act_led#, and fdx_led# outputs can be forced off (1 value) by writing a 10 to bit 5 and 4 of shadow register 1ah. separate 100base-tx and 10-base-t link when bit 12 of register 1dh is set to 1, lnkled# indica tes the link at 100base-tx and spdled# indicates the link at 10base-t. table 4: 10base-t serial mode (7-wire) signals 5220 kpt pin label type description 57 txd (0) i serial transmit data 53 txc o transmit data clock (10 mhz) 56 txen i transmit enable 48 rxd (0) o serial receive data 50 rxc o receive data clock (10 mhz) 62 crs o carrier sense 61 col/rxen o collision detect
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 16 energy detection document 5220-ds04-405-r i nterrupt m ode the bcm5220 can be programmed to provide an interrupt output. three conditions can cause an interrupt to be generated: changes in the duplex mode, changes in the speed of operation or changes in the link status. the interrupt feature is disabled by default. when the interrupt capability is enabled by setting mii register 1ah, bit 14, the xmtled# pin becomes the intr# pin and the rcvled# pin becomes an activity pin named actled#. the intr# pin is open-drain and can be wire-ored with intr# pins of other chips on a board. the status of each interrupt source is reflected in register 1ah, bits 1, 2 and 3. i f any type of interrupt occurs, the interrupt status bit, register 1ah, bit 0, is set. the interrupt register (1ah) also contains several bits to control different facets of the interrupt function. if the interrupt enable bit is set to 0, no status bits are set and no interrupts are generated. if the interrupt enable bit is set to 1, the following conditions apply: if mask status bits (bits 9,10,11) are set to 0 and the interrupt mask (bit 8) is set to 0, status bits and interrupts are available. if mask status bits (bits 9,10,11) are set to 0 and the interrupt mask (bit 8) is set to 1, status bits are set but no interrup ts generated. if any mask status bit is set to 1 and the interrupt mask is set to 0, that status bit is not set and no interrupt of that type is generated. if any mask status bit is set to 1 and the interrupt mask is set to 1, that status bit is not set and no interrupt of any kind is generated. e nergy d etection an on-chip energy detection circuit can determine when a link partner is connected to the end of the transmission media. the circuit monitors the receive inputs for any type of energy, including 10base-t, 100base-tx or 100base-fx packets, and 10base-t or auto-negotiation link pulses. when energy is detected on the receive inputs for longer than 1.3 ms, the energydet output is asserted. if all traces of energy disappear for longer then 1.3s, it is assumed that the link partner has disconnected, and the energydet output is deasserted. the energy detection circuit is operational in both full power and some of the low power modes.
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auto power-down mode page 17 p ower s aving m odes several power saving modes are implemented in the bcm5220, which target pcmcia and cardbus applications. table 5 on page 17 shows low power modes available in the bcm5220. low power modes can be achieved either by hardware pin or mii register programming. the table shows both hardware pin and software bits that determine the low power modes and whether the bcm5220 keeps the clocks and the energy detect circuitry active. the bcm5220 requires a hard reset for a minimum of 20 s to return to normal mode from a low power mode if the clocks are not running. allow at least 2 ms before resuming normal operation with the bcm5220 after the device is set to run in normal mode from a low power mode. it is necessary to choose an appropriate low power mode if the energy detection function support is required while the bcm5220 is in low power mode. a uto p ower -d own m ode in addition to various low power modes shown in table 5, the bcm5220 also supports a special low power mode called auto power down mode. auto power down mode is enabled by setting bit 5 of shadow register 1bh. when in this mode, the bcm5220 automatically enters the low power mode if the energy from the link partner is lost. similarly, the next time energy is detected, the chip resumes full power mode. when the bcm5220 is in this low power mode, it wakes up after 2.5/5.0s (approximately), as determined by bit 4 of shadow register 1b h, and send link pulse while monitoring energy from the link partner. if energy is detected, the bcm5220 enters full power mode and establishes link with the link partner. otherwise, the wake-up mode continues for a duration of 40-600 ms (approximately) as determined by bits [3:0] of shadow register 1bh before going to low power mode. see the shadow register, table 8 on page 23, for a details of various bits. table 5: low power modes low_pwr reset# force iddq low_pwr mode enable clock clocks energy detect x0xxxoffoff 010 0 xrunon xx1 x xoffoff 110 0 0offon 110 0 1runon 010 1 0offon 010 1 1runon low_pwr: pin-16 (BCM5220KPT), pin-f1 (bcm5220kpb) reset#: pin-9 (BCM5220KPT), pin-d2 (bcm5220kpb) force iddq: bit-0 of shadow register 1ah low pwr mode: bit-1 of shadow register 1ah enable clock: bit-2 of shadow register 1ah x = 1/0 or don?t care
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 18 media independent interface (mii) management inte rface: register programming document 5220-ds04-405-r section 5: register summary m edia i ndependent i nterface (mii) m anagement i nterface : r egister p rogramming the bcm5220 fully complies with the ieee 802.3u media independent interface (mii) specification. the mii management interface registers are serially written to and read from using the mdio and mdc pins. a single clock waveform must be provided to the bcm5220 at a rate of 0?25mhz through the mdc pin. the serial data is communicated on the mdio pin. every mdio bit must have the same period as the mdc clock. the mdio bits are latched on the rising edge of the mdc clock. see table 6 for the fields in every mii instruction?s read or write packet frame. preamble (pre) 32 consecutive 1 bits must be sent through the mdio pin to the bcm5220 to signal the beginning of an mii instruction. fewer than 32 1 bits causes the remainder of the instruction to be ignored, unless the preamble suppression mode is enabled (register 01, bit 6). start of frame (st) a 01 pattern indicates that the start of the instruction follows. operation code (op) a read instruction is indicated by 10, while a write instruction is indicated by 01. phy address (phyad) a 5-bit phy address follows next, with the msb transmitted first. the phy address allows a single mdio bus to access multiple transceivers. the bcm5220 supports the full 32-phy address space. register address (regad) a 5-bit register address follows, with the msb transmitted first. the register map of the bcm5220, containing register addresses and bit definitions, are provided on the following pages. table 6: mii management frame format operation pre st op phyad regad ta data idle direction read 1 ... 1 01 10 aaaaa rrrrr zz z0 z ... z d ... d z z driven to bcm5220 driven by bcm5220 write 1 ... 1 01 01 aaaaa rrrrr 10 d ... d z driven to bcm5220
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r media independent interface (mii) m anagement interface: register programming page 19 turnaround (ta) the next two bit times are used to avoid contention on the mdio pin when a read operation is performed. for a write operation, 10 must be sent to the chip during these two bit times. for a read operation, the mdio pin must be placed into high-impedance during these two bit times. the chip drives the mdio pin to 0 during the second bit time. data the last 16 bits of the frame are the actual data bits. for a write operation, these bits are sent to the bcm5220. for a read operation, these bits are driven by the bcm5220. in either case, the msb is transmitted first. when writing to the bcm5220, the data field bits must be stable 10 ns before the rising-edge of mdc, and must be held valid for 10 ns after the rising edge of mdc. when reading from the bcm5220, the data field bits are valid after the rising edge of mdc until the next rising edge of mdc. idle a high-impedance state of the mdio line. all drivers are disabled and the phy?s pull-up resistor pulls the line high. at least one or more clocked idle states are required between frames. following are two examples of mii write and read instructions. to put a chip with phy address 00001 into loopback mode, the following mii write instruction must be issued: 1111 1111 1111 1111 1111 1111 1111 1111 0101 00001 00000 10 0100 0000 0000 0000 1... to determine whether a phy is in the link pass state, the following mii read instruction must be issued: 1111 1111 1111 1111 1111 1111 1111 1111 0110 00001 00001 zz zzzz zzzz zzzz zzzz 1... for the mii read operation, the bcm5220 drives the mdio line during the ta and data fields (the last 17 bit times). a final 65 th clock pulse must be sent to close the transaction and cause a write operation.
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 20 media independent interface (mii) management inte rface: register programming document 5220-ds04-405-r mii r egister m ap s ummary table 7 contains the mii register summary for the bcm5220. the register addresses are specified in hex form, and the name of register bits have been abbreviated. when writing to any register, preserve existing values of the reserved bits by completing a ?read/modify write.? ignore reserved bits when reading registers. never write to an undefined register. the reset values of the registers are shown in the init column. some of these values could be different depending on how the device is configured and also depending on the device revision value.
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r media independent interface (mii) m anagement interface: register programming page 21 table 7: mii register map summary addr name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 init 00h control soft reset loopbac k force100 autoneg enable power down isolate restart autoneg full duplex collision test reserved 3000h 01h status t4 capable tx fdx capable tx capable bt fdx capable 10bt capable reserved mf pream suppress autoneg comp remote fault autoneg capable link status jabber detect extd reg capable 7809h 02hphyid high000 0000001 0000 0 00040h 03h phyid low 0 1 1 0 0 0 011 model# 110 revision # 0 0 0 0 61e0h 04h autoneg advertise next page reserve d remote fault reserved tech pause adv t4 adv tx fdx adv tx adv bt fdx adv bt advertised selector field [4:0] 0 0 0 0 1 01e1h 05h link partner ability lp next page lpackno wlge lp rem fault reserved tech lp pause lp t4 lp tx fdx lp tx lp bt fdx lp bt link partner selector field [4:0] 0000h 06h autoneg expansion reserved par det fault lp next pg able next pg able page recvd lp auto neg able 0004h 07h next page next page reserve d message page acknowledge2 toggle message/unformatted code field 2001h 08h lp next page next page reserve d message page acknowledge2 toggle message/unformatted code field 0000h 10h 100base-x aux control reserved trans disable reserved bypass 4b5b enc/dec bypass scram/ descram bypass nrzi enc/dec bypass rcv sym align baseline wander disable fef enable reserved 0000h 11h 100base-x aux status - reserved fxmode locked current 100link status current remote fault reserved false carrier detected bad esd detected rcv error detected xmterror detected lockerror detected mlt3 error detected 0000h 12h 100base-x rcv error counter receive error counter [15:0] 0000h 13h 100base-x false carrier counter reserved false carrier sense counter [7:0] 0000h
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 22 media independent interface (mii) management inte rface: register programming document 5220-ds04-405-r 14h 100base-x disconnect counter reserved 0200h 15h reserved reserved 0300h 16h reserved reserved 0000h 17h ptest reserved 0000h 18h auxiliary control/ status jabber disable force link reserved hsq lsq edge rate [1:0] autoneg enable indicator force 100 indicator sp100 indicator fdx indicator 003xh 19h auxiliary status summary autoneg complet e autoneg com- pleteack autoneg ack detect autoneg ability detect autoneg pause autoneg hcd autoneg pardet fault lp remote fault lp page rcvd lp autoneg able sp100 indicator link status internal autoneg enabled jabber detect 0000h 1ah interrupt fdx led enable intr enable reserved fdx mask spd mask link mask intr mask reserved fdx change spd change link change intr status 9f0xh 1bh auxiliary mode2 reserved 10bt dribble correct token ring mode hstr fifo enable reserve d block 10bt echo mode traffic meter led mode activity led force on reserve d sqe disable activity/ link led enable qual parallel detect mode reserve d 008ah 1ch 10base-t aux. error & general status reserved manchstr code err (bt) eof err (bt) reserve d 00 1reserve d autoneg enable indicator force 100 indicator sp100 indicator fdx indicator 002xh 1dh auxiliary mode reserved alt link mode reserved activity led force inactive link led force inactive reserved block txen mode reserve d x000h 1eh auxiliary multi-phy hcd tx fdx hc t4 hcd tx hcd 10bt fdx hcd 10bt reserved restart autoneg autoneg complet e reserved ack detect ability detect super isolate reserved 10bt serial mode rxer code mode 0000h 1fh broadcom test reserved shadow register enable reserved 000bh table 7: mii register map summary (cont.) addr name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 init
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r media independent interface (mii) m anagement interface: register programming page 23 table 8: mii shadow register map summary addr name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 init 18h reserved reserved 003ah 1ah auxiliary mode 4 reserved led force [1:0] reserve d enable clocks during low pwr mode force low pwr mode force iddq mode 3000h 1bh auxiliary status 2 mlt3 detect reserved apd enable apd sleep timer apd wake-up timer [3:0] 0001h 1ch auxiliary status 3 reserved flp detect nlp detect link break timer expire linkfail timer expire fifo comsumption[3:0] 0000h 1dh auxiliary mode 3 reserved fifo size select [3:0] 0c04h 1eh auxiliary status4 packet length counter [15:0] 0000h
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 24 media independent interface (mii) management inte rface: register programming document 5220-ds04-405-r mii c ontrol r egister the mii control register bit descriptions are shown in table 9. reset to reset the bcm5220 by software control, a 1 must be written to bit 15 of the control register using an mii write operation. the bit clears itself after the reset process is complete, and need not be cleared using a second mii write. writes to other control register bits have no effect until the reset process is completed, which requires approximately 1 microsecond. writing a 0 to this bit has no effect. since this bit is self-clearing, after a few cycles from a write operation, it returns a 0 when read. loopback the bcm5220 may be placed into loopback mode by writing a 1 to bit 14 of the control register. clear the loopback mode by writing a 0 to bit 14 of the control register, or by resetting the chip. when this bit is read, it returns a 1 when the chip is in loopback mode, otherwise it returns a 0. forced speed selection if auto-negotiation is enabled (both auto-negotiation pin and bit are enabled) or disabled by hardware control (auto- negotiation pin is pulled-low), this bit has no effect on the speed selection. however, if auto-negotiation is disabled by software control, the operating speed of the bcm5220 can be forced by writing the appropriate value to bit 13 of the control register. writing a 1 to this bit forces 100base-x operation, while writing a 0 forces 10base-t operation. when this bit is read, it returns the value of the software-controlled forced speed selection only. to read the overall state of forced speed selection, including both hardware and software control, use bit 2 of the auxiliary control register (18h). table 9: mii control register (address 00000b, 0d, 00h) bit name r/w description default 15 soft reset r/w (sc) 1 = phy reset 0 = normal operation 0 14 loopback r/w 1 = loopback mode 0 = normal operation 0 13 forced speed selection r/w 1 = 100 mbps 0 = 10 mbps 1 12 auto-negotiation enable r/w 1 = auto-negotiation enable 0 = auto-negotiation disable 1 11 power down ro 0 = normal operation 0 10 reserved a r/w - 0 9 restart auto-negotiation r/w (sc) 1 = restart auto-negotiation process 0 = normal operation 0 8 duplex mode r/w 1 = full-duplex 0 = half-duplex 0 7 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? -- 0 6:0 reserved a -- 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high (ll and lh are cleared after read operation)
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r media independent interface (mii) m anagement interface: register programming page 25 auto-negotiation enable auto-negotiation can be disabled by one of two methods: hardware or software control. if the anen input pin is driven to a logic 0, auto-negotiation is disabled by hardware control. if bit 12 of the control register is written with a value of 0, auto - negotiation is disabled by software control. when auto-negotiation is disabled in this manner, writing a 1 to the same bit of the control register or resetting the chip re-enables auto-negotiation. writing to this bit has no effect when auto-negotiation has been disabled by hardware control. when read, this bit returns the value most recently written to this location, or 1 if it has not been written since the last chip reset. power down the power modes of the bcm5220 are not accessible by this mii register bit. use lowpwr pin control instead. isolate the phy can be isolated from its media independent interface by writing a 1 to bit 10 of the control register. all mii outputs are tri-stated and all mii inputs are ignored. because the mii management interface is still active, the isolate mode can be cleared by writing a 0 to bit 10 of the control register, or by resetting the chip. when this bit is read, it returns a 1 when the chip is in isolate mode; otherwise it returns a 0. restart auto-negotiation bit 9 of the control register is a self-clearing bit that allows the auto-negotiation process to be restarted, regardless of th e current status of the auto-negotiation state machine. for this bit to have an effect, auto-negotiation must be enabled. writing a 1 to this bit restarts the auto-negotiation, while writing a 0 to this bit has no effect. because the bit is self-clearing af ter only a few cycles, it always returns a 0 when read. the operation of this bit is identical to bit 8 of the auxiliary multiple phy re gister (1eh). duplex mode by default, the bcm5220 powers up in half-duplex mode. the chip can be forced into full-duplex mode by writing a 1 to bit 8 of the control register while auto-negotiation is disabled. half-duplex mode can be resumed by writing a 0 to bit 8 of the control register, or by resetting the chip. collision test test the col pin by activating the collision test mode. while in this mode, asserting txen causes the col output to go high within 512 bit times. deasserting txen causes the col output to go low within 4 bit times. writing a 1 to bit 7 of the control register enables the collision test mode. writing a 0 to this bit or resetting the chip disables the collision test mode. when this bit is read, it returns a 1 when the collision test mode has been enabled; otherwise it returns a 0. this bit should only be set while in loopback test mode. reserved bits all reserved mii register bits must be written as 0 at all times. ignore the bcm5220 output when these bits are read.
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 26 mii status register document 5220-ds04-405-r mii s tatus r egister the mii status register bit descriptions are shown in table 10. 100base-t4 capability the bcm5220 is not capable of 100base-t4 operation, and returns a 0 when bit 15 of the status register is read. 100base-x full-duplex capability the bcm5220 is capable of 100base-x full-duplex operation, and returns a 1 when bit 14 of the status register is read. 100base-x half-duplex capability the bcm5220 is capable of 100base-x half-duplex operation, and returns a 1 when bit 13 of the status register is read. 10base-t full-duplex capability the bcm5220 is capable of 10base-t full-duplex operation, and returns a 1 when bit 12 of the status register is read. table 10: mii status register (address 00001b, 01d, 01h) bit name r/w description default 15 100base-t4 capability ro 0 = not 100base-t4 capable 0 14 100base-tx fdx capability ro 1 = 100base-tx full-duplex capable 1 13 100base-tx capability ro 1 = 100base-tx half-duplex capable 1 12 10base-t fdx capability ro 1 = 10base-t full-duplex capable 1 11 10base-t capability ro 1 = 10base-t half-duplex capable 1 10:7 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ro ignore when read ignore when read 0 6 mf preamble suppression r/w 1 = preamble may be suppressed 0 = preamble always required 0 5 auto-negotiation complete ro 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 0 4 remote fault ro 1 = far-end fault condition detected 0 = no far-end fault condition detected 0 3 auto-negotiation capability ro 1 = auto-negotiation capable 0 = not auto-negotiation capable 1 2link status ro ll 1 = link is up (link pass state) 0 = link is down (link fail state) 0 1 jabber detect ro ll 1 = jabber condition detected 0 = no jabber condition detected 0 0 extended capability ro 1 = extended register capable 1 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high (ll and lh are cleared after read operation)
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r mii status register page 27 10base-t half-duplex capability the bcm5220 is capable of 10base-t half-duplex operation, and returns a 1 when bit 11 of the status register is read. reserved bits ignore the bcm5220 output when these bits are read. preamble suppression this bit is the only writable bit in the status register. setting this bit to a 1 allows subsequent mii management frames to be accepted with or without the standard preamble pattern. when preamble suppression is enabled, only 2 preamble bits are required between successive management commands, instead of the normal 32. auto-negotiation complete returns a 1 if auto-negotiation process has been completed and the contents of registers 4, 5, and 6 are valid. remote fault the phy returns a 1 on bit 4 of the status register when its link partner has signalled a far-end fault condition. when a far- end fault occurs, the bit is latched at 1 and remains so until the register is read and the remote fault condition has been cleared. auto-negotiation capability the bcm5220 is capable of performing ieee auto-negotiation, and returns a 1 when bit 4 of the status register is read, regardless of whether the auto-negotiation function has been disabled. link status the bcm5220 returns a 1 on bit 2 of the status register when the link state machine is in link pass, indicating that a valid link has been established. otherwise, it returns 0. when a link failure occurs after the link pass state has been entered, the link status bit is etched at 0 and remains so until the bit is read. after the bit is read, it becomes 1 when the link pass sta te is entered again. jabber detect 10base-t operation only. the bcm5220 returns a 1 on bit 1 of the status register if a jabber condition has been detected. after the bit is read once, or if the chip is reset, it reverts to 0. extended capability the bcm5220 supports extended capability registers, and returns a 1 when bit 0 of the status register is read. several extended registers have been implemented in the bcm5220, and their bit functions are defined later in this section.
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 28 mii status register document 5220-ds04-405-r phy i dentifier r egisters the physical identifier registers bit descriptions are shown in table 11. broadcom corporation has been issued an organizationally unique identifier (oui) by the ieee. it is a 24-bit number, 00- 10-18, expressed as hex values. that number, along with the broadcom model number for the bcm5220 part, 1eh, and broadcom revision number, 0h for the a0 is placed into two mii registers. the translation from oui, model number and revision number to phy identifier register occurs as follows: phyid high [15:0] = oui[21:6] phy low [15:0] = oui[5:0] + model[5:0] + rev[3:0] the 2 most significant bits of the oui are not represented (oui[23:22]). table 11 shows the result of concatenating these values to form mii identifier registers phyid high and phyid low. table 11: phy identifier registers (addresses 00010 and 00011b, 02 and 03b, 02 and 03h) bit name r/w description value 15:0 mii address 02h ro phyid high 0040h 15:0 mii address 03h ro phyid low 61e0h
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r mii status register page 29 a uto -n egotiation a dvertisement r egister next page the bcm5220 supports the next page function. reserved bits ignore output when read. remote fault writing a 1 to bit 13 of the advertisement register causes a remote fault indicator to be sent to the link partner during auto- negotiation. writing a 0 to this bit or resetting the chip clears the remote fault transmission bit. this bit returns the value last written to it, or else 0 if no write has been completed since the last chip reset. reserved technologies bits ignore output when read. pause pause operation for full-duplex links. the use of this bit is independent of the negotiated data rate, medium, or link technology. the setting of this bit indicates the availability of additional dte capability when full-duplex operation is in us e. this bit is used by one mac to communicate pause capability to its link partner and has no effect on phy operation. table 12: auto-negotiation advertisement register (address 04d, 04h) bit name r/w description default 15 next page r/w 1 = next page ability is enabled 0 = next page ability is disabled 0 14 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ro ignore when read 13 remote fault r/w 1 = transmit remote fault 0 12:11 reserved technologies ro ignore when read 00 10 pause r/w 1 = pause operation for full-duplex 0 9 advertise 100base-t4 r/w 1 = advertise t4 capability 0 = do not advertise t4 capability 0 8 advertise 100base-x fdx r/w 1 = advertise 100base-x full-duplex 0 = do not advertise 100base-x full-duplex 1 7 advertise 100base-x r/w 1 = advertise 100base-x 1 6 advertise 10base-t fdx r/w 1 = advertise 10base-t full-duplex 0 = do not advertise 10base-t full-duplex 1 5 advertise 10base-t r/w 1 = advertise 10base-t 1 4:0 advertise selector field r/w indicates 802.3 00001 notes: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 30 mii status register document 5220-ds04-405-r advertisement bits use bits 9:5 of the advertisement register to customize the ability information transmitted to the link partner. the default value for each bit reflects the abilities of the bcm5220. by writing a 1 to any of the bits, the corresponding ability can be transmitted to the link partner. writing a 0 to any bit causes the corresponding ability to be suppressed from transmission. resetting the chip restores the default bit values. reading the register returns the values last written to the corresponding bits, or else the default values if no write has been completed since the last chip reset. selector field bits 4:0 of the advertisement register contain the value 00001, indicating that the chip belongs to the 802.3 class of phy transceivers.
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r mii status register page 31 a uto -n egotiation l ink p artner (lp) a bility r egister the values contained in the auto-negotiation link partner ability register are only guaranteed to be valid after auto- negotiation has successfully completed, as indicated by bit 5 of the mii status register. lp next page bit 15 of the link partner ability register returns a value of 1 when the link partner implements the next page function and has next page information that it wants to transmit. the bcm5220 does not implement the next page function, and thus ignores the next page bit, except to copy it to this register. lp acknowledge bit 14 of the link partner ability register is used by auto-negotiation to indicate that a device has successfully received its link partner?s link code word. lp remote fault bit 13 of the link partner ability register returns a value of 1 when the link partner signals that a remote fault has occurred . the bcm5220 simply copies the value to this register and does not act upon it. reserved bits ignore when read. lp advertise pause indicates that the link partner pause bit is set. table 13: auto-negotiation link partner ability register (address 05d, 05h) bit name r/w description default 15 lp next page ro link partner next page bit 0 14 lp acknowledge ro link partner acknowledge bit 0 13 lp remote fault ro link partner remote fault indicator 0 12:11 reserved technologies ro ignore when read 000 10 lp advertise pause ro link partner has pause capability 0 9 lp advertise 100base-t4 ro link partner has 100base-t4 capability 0 8 lp advertise 100base-x fdx ro link partner has 100base-x fdx capability 0 7 lp advertise 100base-x ro link partner has 100base-x capability 0 6 lp advertise 10base-t fdx ro link partner has 10base-t fdx capability 0 5 lp advertise 10base-t ro link partner has 10base-t capability 0 4:0 link partner selector field ro link partner selector field 00000 notes: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 32 mii status register document 5220-ds04-405-r lp advertise bits bits 9:5 of the link partner ability register reflect the abilities of the link partner. a 1 on any of these bits indicates tha t the link partner is capable of performing the corresponding mode of operation. bits 9:5 are cleared any time auto-negotiation is restarted or the bcm5220 is reset. lp selector field bits 4:0 of the link partner ability register reflect the value of the link partner?s selector field. these bits are cleared an y time auto-negotiation is restarted or the chip is reset.
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r mii status register page 33 a uto -n egotiation e xpansion r egister table 14 shows the auto-negotiation expansion register bit descriptions. reserved bits ignore when read. parallel detection fault bit 4 of the auto-negotiation expansion register is a read-only bit that gets latched high when a parallel detection fault occu rs in the auto-negotiation state machine. for further details, refer to the ieee standard. the bit is reset to 0 after the registe r is read, or when the chip is reset. link partner next page able bit 3 of the auto-negotiation expansion register returns a 1 when the link partner has next page capabilities. it has the same value as bit 15 of the link partner ability register. next page able the bcm5220 returns 1 when bit 2 of the auto-negotiation expansion register is read, indicating that it has next page capabilities. page received bit 1 of the auto-negotiation expansion register is latched high when a new link code word is received from the link partner, checked, and acknowledged. it remains high until the register is read, or until the chip is reset. table 14: auto-negotiation expansion register (address 00110b, 6d, 06h) bit name r/w description default 15:5 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ro ignore when read 4 parallel detection fault ro lh 1 = parallel detection fault 0 = no parallel detection fault 0 3 link partner next page able ro 1 = link partner has next page capability 0 = link partner does not have next page 0 2 next page able ro 1 = bcm5220 does have next page capability 1 1 page received ro 1 = new page has been received 0 = new page has not been received 0 0 link partner auto- negotiation able ro lh 1 = link partner has auto-negotiation capability 0 = link partner does not have auto-negotiation 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high (ll and lh are cleared after read operation)
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 34 mii status register document 5220-ds04-405-r link partner auto-negotiation able bit 0 of the auto-negotiation expansion register returns a 1 when the link partner is known to have auto-negotiation capability. before any auto-negotiation information is exchanged, or if the link partner does not comply with ieee auto- negotiation, the bit returns a value of 0.
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r mii status register page 35 a uto -n egotiation n ext p age r egister next page indicates whether this is the last next page to be transmitted. message page differentiates a message page from an unformatted page. acknowledge 2 indicates that a device has the ability to comply with the message. toggle used by the arbitration function to ensure synchronization with the link partner during next page exchange. message code field an 11-bit-wide field encoding 2048 possible messages. unformatted code field an 11-bit-wide field, which may contain an arbitrary value. table 15: next page transmit register (address 07d, 07h) bit name r/w description default 15 next page r/w 1 = additional next page(s) will follow 0 = last page 0 14 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? r/w ignore when read 0 13 message page r/w 1= message page 0 = unformatted page 1 12 acknowledge 2 r/w 1 = will comply with message 0 = cannot comply with message 0 11 toggle ro 1 = previous value of the transmitted link code word equalled logic zero 0 = previous value of the transmitted link code word equalled logic one 0 10:0 message/unformatted code field r/w 1 notes: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 36 auto-negotiation link partner (lp) ne xt page transmit register document 5220-ds04-405-r a uto -n egotiation l ink p artner (lp) n ext p age t ransmit r egister next page indicates whether this is the last next page. message page differentiates a message page from an unformatted page. acknowledge 2 indicates that link partner has the ability to comply with the message. toggle used by the arbitration function to ensure synchronization with the link partner during next page exchange. message code field an 11-bit-wide field encoding 2048 possible messages. unformatted code field an 11-bit-wide field, which may contain an arbitrary value. table 16: next page transmit register (address 08d, 08h) bit name r/w description default 15 next page ro 1 = additional next page(s) will follow 0 = last page 0 14 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ro ignore when read 0 13 message page ro 1= message page 0 = unformatted page 0 12 acknowledge 2 ro 1 = will comply with message 0 = cannot comply with message 0 11 toggle ro 1 = previous value of the transmitted link code word equalled logic zero 0 = previous value of the transmitted link code word equalled logic one 0 10:0 message/unformatted code field ro 0 notes: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auto-negotiation link partner (lp) next page transmit register page 37 100base-x a uxiliary c ontrol r egister transmit disable the transmitter can be disabled by writing a 1 to bit 13 of mii register 10h. the transmitter output (td) is forced into a hig h impedance state. bypass 4b5b encoder/decoder the 4b5b encoder and decoder can be bypassed by writing a 1 to bit 10 of mii register 10h. the transmitter sends 5b codes from the txer and txd3, txd2, txd1,txd0 pins directly to the scrambler. txen must be active and frame encapsulation (insertion of j/k and t/r codes) is not performed. the receiver places descrambled and aligned 5b codes onto the rxer, rxd3, rxd2, rxd1 and rxd0 pins. crs can be asserted when a valid frame is received. bypass scrambler/descrambler the stream cipher function can be disabled by writing a 1 to bit 9 of mii register 10h. the stream cipher function is re-enable d by writing a 0 to this bit. table 17: 100base-x auxiliary control register (address 16d, 10h) bit name r/w description default 15:14 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? write as 0, ignore when read 0 13 transmit disable r/w 1 = transmitter disabled in phy 0 = normal operation 0 12 reserved a r/w write as 0, ignore when read 0 11 reserved a write as 0, ignore when read 0 10 reserved a r/w write as 0, ignore when read 0 9 bypass scrambler/ descrambler r/w 1 = scrambler and descrambler disabled 0 = scrambler and descrambler enabled 0 8 bypass nrzi encoder/ decoder r/w 1 = nrzi encoder and decoder is disabled 0 = nrzi encoder and decoder is enabled 0 7 bypass receive symbol alignment r/w 1 = 5b receive symbols not aligned 0 = receive symbols aligned to 5b boundaries 0 6 baseline wander correction disable r/w 1 = baseline wander correction disabled 0 = baseline wander correction enabled 0 5 fef enable r/w 1 = far end fault enabled 0 = far end fault disabled 0 4:3 reserved a r/w write as 0, ignore when read 0 2 extended fifo enable r/w 1 = extended fifo mode, 0 = normal fifo mode 0 1 reserved a r/w write as 0, ignore when read 0 0 reserved a r/w write as 0, ignore when read 0 notes: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 38 auto-negotiation link partner (lp) ne xt page transmit register document 5220-ds04-405-r bypass nrzi encoder/decoder the nrzi encoder and decoder can be bypassed by writing a 1 to bit 8 of mii register 10h, causing 3-level nrz data to be transmitted and received on the cable. normal operation (3-level nrzi encoding and decoding) can be re-enabled by writing a 0 to this bit. bypass receive symbol alignment receive symbol alignment can be bypassed by writing a 1 to bit 7 of mii register 10h. when used in conjunction with the bypass 4b5b encoder/decoder bit, unaligned 5b codes are placed directly on the rxer and rxd1, rxd0 pins. baseline wander correction disable the baseline wander correction circuit can be disabled by writing a 1 to bit 6 of mii register 10h. the bcm5220 corrects for baseline wander on the receive data signal when this bit is cleared. fef enable controls the far end fault mechanism associated with 100base-fx operation. a 1 enables the fef function and a 0 disables it. reserved bits the reserved bits of the 100base-x auxiliary control register must be written as 0 at all times. ignore the bcm5220 outputs when these bits are read.
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auto-negotiation link partner (lp) next page transmit register page 39 100base-x a uxiliary s tatus r egister fx mode returns a value derived from the sd input pins. returns 1 when sd+ are driven with a valid differential signal level. returns 0 when both sd+ and sd- are simultaneously driven low. locked the phy returns a 1 in bit 9 when the descrambler is locked to the incoming data stream. otherwise it returns a 0. current 100base-x link status the phy returns a 1 in bit 8 when the 100base-x link status is good. otherwise it returns a 0. remote fault the phy returns a 1 while its link partner is signalling a far-end fault condition. otherwise it returns a 0. table 18: 100base-x auxiliary status register (address 17d, 11h) bit name r/w description default 15:12 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ro ignore when read 0 11 reserved a ro ignore when read 0 10 fx mode ro 1 = 100base-fx mode 0 = 100base-tx or 10base-t mode pin 9 locked ro 1 = descrambler locked 0 = descrambler unlocked 0 8 current 100base-x link status ro 1 = link pass 0 = link fail 0 7 remote fault ro 1 = remote fault detected 0 = no remote fault detected 0 6 reserved a ro ignore when read 0 5 false carrier detected ro lh 1 = false carrier detected since last read 0 = no false carrier since last read 0 4 bad esd detected ro lh 1 = esd error detected since last read 0 = no esd error since last read 0 3 receive error detected ro lh 1 = receive error detected since last read 0 = no receive error since last read 0 2 transmit error detected ro lh 1 = transmit error code received since last read 0 = no transmit error code received since last read 0 1 lock error detected ro lh 1 = lock error detected since last read 0 = no lock error since last read 0 0 mlt3 code error detected ro lh 1 = mlt3 code error detected since last read 0 = no mlt3 code error since last read 0 notes: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 40 auto-negotiation link partner (lp) ne xt page transmit register document 5220-ds04-405-r false carrier detected the phy returns a 1 in bit 5 of the extended status register if a false carrier has been detected since the last time this regi ster was read. otherwise it returns a 0. bad esd detected the phy returns a 1 in bit 4 if an end of stream delimiter error has been detected since the last time this register was read. otherwise it returns a 0. receive error detected the phy returns a 1 in bit 3 if a packet was received with an invalid code since the last time this register was read. otherwis e it returns a 0. transmit error detected the phy returns a 1 in bit 2 if a packet was received with a transmit error code since the last time this register was read. otherwise it returns a 0. lock error detected the phy returns a 1 in bit 1 if the descrambler has lost lock since the last time this register was read. otherwise it returns a 0. mlt3 code error detected the phy returns a 1 in bit 0 if an mlt3 coding error has been detected in the receive data stream since the last time this register was read. otherwise it returns a 0.
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auto-negotiation link partner (lp) next page transmit register page 41 100base-x r eceive e rror c ounter receive error counter [15:0] this counter increments each time the bcm5220 receives a non-collision packet containing at least one receive error. the counter automatically clears itself when read. when the counter reaches its maximum value, ffh, it stops counting receive errors until cleared. table 19: 100base-x receive error c ounter (address 18d, 12h) bit name r/w description default 15:8 receive error counter r/w write as 0, ignore when read 0000h 7:0 receive error counter r/w number of non-collision packets with receive errors since last read 0000h
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 42 100base-x disconnect counter document 5220-ds04-405-r 100base-x f alse c arrier s ense c ounter false carrier sense counter [7:0] this counter increments each time the bcm5220 detects a false carrier on the receive input. this counter automatically clears itself when read. when the counter reaches its maximum value, ffh, it stops counting false carrier sense errors until cleared. 100base-x d isconnect c ounter p test r egister the bit description for the ptest register is shown in table 22. table 20: 100base-x false carrier sense counter (address 19d, 13h) bit name r/w description default 15:8 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? r/w write as 0, ignore when read 00h 7:0 false carrier sense counter r/w number of false carrier sense events since last read 00h table 21: 100base-x disconnect counter (address 20d, 14h) bit name r/w description default 15 reserved a r/o 0 = normal 0 14 reserved a r/o 0 = normal 0 13:8 reserved a r/w write as 000010, ignore when read 000010 7:0 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? r/w write as 00h, ignore when read 00h notes: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). table 22: ptest register (address 10111b, 23d, 17h) bit name r/w description default 15:0 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ro ignore when read 0000h
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auxiliary control/status register page 43 a uxiliary c ontrol /s tatus r egister the auxiliary control/status register bit descriptions are shown in table 23. jabber disable 10base-t operation only. bit 15 of the auxiliary control register allows the user to disable the jabber detect function, define d in the ieee standard. this function shuts off the transmitter when a transmission request has exceeded a maximum time limit. by writing a 1 to bit 15 of the auxiliary control register, the jabber detect function is disabled. writing a 0 to this bit or resetting the chip restores normal operation. reading this bit returns the value of jabber detect disable. link force writing a 1 to bit 14 of the auxiliary control register allows the user to disable the link integrity state machines, and place the bcm5220 into forced link pass status. writing a 0 to this bit or resetting the chip restores the link integrity functions. reading this bit returns the value of the force link bit. hsq and lsq extend or decrease the squelch levels for detection of incoming 10base-t data packets. the default squelch levels implemented are those defined in the ieee standard. the high-and low-squelch levels are useful for situations where the ieee-prescribed levels are inadequate. the squelch levels are used by the crs/link block to filter out noise and recognize only valid packet preambles and link integrity pulses. extending the squelch levels allows the bcm5220 to operate properly table 23: auxiliary control/status register (address 24d, 18h) bit name r/w description default 15 jabber disable r/w 1 = jabber function disabled 0 = jabber function enabled 0 14 force link r/w 1 = force 10base-t link pass 0 = normal 10base-t link operation 0 13:8 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ro ignore when read 000000 7:6 hsq : lsq r/w these two bits define the squelch mode of the 10base-t carrier sense mechanism 00 = normal squelch 01 = low squelch 10 = high squelch 11 = not allowed 00 5:4 edge rate [1:0] r/w 00 = 1 ns 01 = 2 ns 10 = 3 ns 11 = 4 ns 11 3 auto-negotiation indication ro 1 = auto-negotiation activated 0 = speed forced manually anen pin 2 force 100/10 indication ro 1 = speed forced to 100base-x 0 = speed forced to 10base-t f100 pin 1 speed indication ro 1 = 100base-x 0 = 10base-t 0 full-duplex indication ro 1 = full-duplex active 0 = full-duplex not active fdx pin
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 44 auxiliary control/status register document 5220-ds04-405-r over longer cable lengths. decreasing the squelch levels can be useful in situations where there is a high level of noise present on the cables. reading these 2 bits returns the value of the squelch levels. edge rate control bits used to program the transmit dac output edge rate in 100base-tx mode. a larger value on these bits produces slower transitions on the transmit waveform. auto-negotiation indication this read-only bit indicates whether auto-negotiation has been enabled or disabled on the bcm5220. a combination of a 1 in bit 12 of the control register and a logic 1 on the an en input pin is required to enable auto-negotiation. when auto- negotiation is disabled, bit 3 of the auxiliary control register (18h) returns a 0. at all other times, it returns a 1. force100/10 indication this read-only bit returns a value of 0 when one of following cases is true: the anen pin is low and the f100 pin is low. the anen pin is high and bit 12 of the control register has been written 0 and bit 13 of the control register has been written 0. when bit 2 of the auxiliary control register (18h) is 0, the speed of the chip is 10base-t. in all other cases, either the spee d is not forced (auto-negotiation is enabled), or the speed is forced to 100base-x. speed indication this read-only bit shows the true current operation speed of the bcm5220. a 1 indicates 100base-x operation, and a 0 indicates 10base-t. while the auto-negotiation exchange is performed, the bcm5201 is always operating at 10base-t speed. full-duplex indication this read-only bit returns a 1 when the bcm5220 is in full-duplex mode. in all other modes, it returns a 0.
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auxiliary control/status register page 45 a uxiliary s tatus s ummary r egister the auxiliary status summary register contains copies of redundant status bits found elsewhere within the mii register space. descriptions for each of these individual bits can be found associated with their primary register descriptions. table 24 indicates the bits found in this register. table 24: auxiliary status summary register (address 25d, 19h) bit name r/w description default 15 auto-negotiation complete ro 1 = auto-negotiation process completed 0 14 auto-negotiation complete acknowledge ro lh 1 = auto-negotiation completed acknowledge state 0 13 auto-negotiation acknowledge detected ro lh 1 = auto-negotiation acknowledge detected 0 12 auto-negotiation ability detect ro lh 1 = auto-negotiation for link partner ability 0 11 auto-negotiation pause ro bcm5220 and link partner pause operation bit 0 10:8 auto-negotiation hcd ro 000 = no highest common denominator 001 = 10base-t 010 = 10base-t full-duplex 011 = 100base-tx 100 = 100base-t4 101 = 100base-tx full-duplex 11x = undefined 000 7 auto-negotiation parallel detection fault ro lh 1 = parallel detection fault 0 6 link partner remote fault ro 1 = link partner remote fault 0 5 link partner page received ro lh 1 = new page has been received 0 4 link partner auto- negotiation able ro 1 = link partner is auto-negotiation capable 0 3 speed indicator ro 1 = 100 mbps 0 = 10 mbps 2 link status ro ll 1 = link is up (link pass state) 0 1 auto-negotiation enabled ro 1 = auto-negotiation enabled anen pin 0 jabber detect ro lh 1 = jabber condition detected 0 note: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high (ll and lh are cleared after read operation)
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 46 auxiliary control/status register document 5220-ds04-405-r i nterrupt r egister fdx led enable when this bit is set to a 1, fdx led pin g7(bga)/34(pqfp) will output fdx status. otherwise, when intr enable is set to a 1 it will output interrupt state. when both bits are 0, it will output xmt state. interrupt enable setting this bit enables interrupt mode. fdx mask when this bit is set, changes in duplex mode will not generate an interrupt. spd mask when this bit is set, changes in operating speed will not generate an interrupt. link mask when this bit is set, changes in link status will not generate an interrupt. table 25: interrupt register (address 26d, 1ah) bit name r/w description default 15 fdx led enable r/w 1 = enable full-duplex led output on g7/34 0 = enable xmtled or interrupt led if interrupt is enabled. 0 14 intr enable r/w interrupt enable 0 13:12 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ro ignore when read 00 11 fdx mask r/w full-duplex interrupt mask 1 10 spd mask r/w speed interrupt mask 1 9 link mask r/w link interrupt mask 1 8 intr mask r/w master interrupt mask 1 7:4 reserved ro ignore when read 000 3 fdx change ro lh duplex change interrupt 0 2 spd change ro lh speed change interrupt 0 1 link change ro lh link change interrupt 0 0 intr status ro lh interrupt status 0 notes: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auxiliary mode 2 register page 47 interrupt mask master interrupt mask. when this bit is set, no interrupts will be generated, regardless of the state of the other mask bits. fdx change a 1 indicates a change of duplex status since last register read. register read clears the bit. spd change a 1 indicates a change of speed status since last register read. register read clears the bit. link change a 1 indicates a change of link status since last register read. register read clears the bit. interrupt status represents status of the intr# pin. a 1 indicates that the interrupt mask is off and that one or more of the change bits are set. register read clears the bit. a uxiliary m ode 2 r egister 10base-t dribble bit correct when enabled, the phy rounds down to the nearest nibble when dribble bits are present on the 10base-t input stream. table 26: auxiliary mode 2 register (address 27d, 1bh) bit name r/w description default 15:12 reserved a ro ignore when read 0 11 10base-t dribble bit correct r/w 1 = enable, 0 = disable 0 10 token ring mode r/w 1 = enable, 0 = disable 0 9 hstr fifo enable r/w 1 = enable, 0 = disable 0 8 reserved a ro ignore when read 0 7 block 10bt echo mode r/w 1 = enable, 0 = disable 1 6 traffic meter led mode r/w 1 = enable, 0 = disable 0 5 activity led force on r/w 1 = on, 0 = normal operation 0 4 reserved a r/w ignore when read 1 3 reserved a r/w write as 1, ignore when read 1 2 activity/link led mode r/w 1 = enable, 0 = disable 0 1 qual parallel detect mode r/w 1 = enable, 0 = disable 1 0 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ro ignore when read 0 notes: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 48 auxiliary mode 2 register document 5220-ds04-405-r token ring mode when enabled, the 100base-x unlock timer changes to allow long packets. block 10base-t echo mode when enabled, during 10base-t half-duplex transmit operation, the txen signal does not echo onto the rxdv pin. the txen echoes onto the crs pin and the crs deassertion directly follows the txen deassertion. traffic meter led mode when enabled, the activity leds (actled# and fdxled# if full-duplex led and interrupt led modes are not enabled) does not blink based on the internal led clock (approximately 80 ms on time). instead, they blink based on the rate of receive and transmit activity. each time a receive or transmit operation occurs, the led turns on for a minimum of 5 ms. during light traffic, the led blinks at a low rate, while during heavier traffic the leds remains on. activity led force on when asserted, the activity leds (actled# and fdxled# if full-duplex led and interrupt led modes are not enabled) is turned on. this bit has a higher priority than the activity led force inactive, bit 4, register 1dh. activity/link led mode when enabled, the rcvled# output goes active upon acquiring link and pulses during receive or transmit activity. qualified parallel detect mode this bit allows the auto-negotiation/parallel detection process to be qualified with information in the advertisement register. if this bit is not set, the local bcm5220 device is enabled to auto-negotiate, and the far-end device is a 10base-t or 100base-x non-auto-negotiating legacy type, the local device auto-negotiate/parallel detects the far-end device, regardless of the contents of its advertisement register (04h). if this bit is set, the local device compares the link speed detected to the contents of its advertisement register. if the particular link speed is enabled in the advertisement register, the local device asserts link. if the link speed is disabled in this register, then the local device does not assert link and continues monitoring for a matching capability link speed.
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auxiliary mode 2 register page 49 10base-t a uxiliary e rror & g eneral s tatus r egister manchester code error indicates that a manchester code violation was received. this bit is only valid during 10base-t operation. end of frame error indicates that the end of frame (eof) sequence was improperly received, or not received at all. this error bit is only valid during 10base-t operation. auto-negotiation indication this read-only bit indicates whether auto-negotiation has been enabled or disabled on the bcm5220. a combination of a 1 in bit 12 of the control register and a logic 1 on the an en input pin is required to enable auto-negotiation. when auto- negotiation is disabled, bit 15 of the auxiliary mode register returns a 0. at all other times, it returns a 1. force 100/10 indication this read-only bit returns a value of 0 when one of following two cases is true: the anen pin is low and the f100 pin is low. (or) bit 12 of the control register has been written 0 and bit 13 of the control register has been written 0. table 27: 10base-t auxiliary error & general status register (address 28d, 1ch) bit name r/w description default 15:11 reserved a ro ignore when read 00001 10 manchester code error ro 1 = manchester code error (10base-t) 0 9 end of frame error ro 1 = eof detection error (10base-t) 0 8 reserved a ro ignore when read 0 7:5 reserved a ro ignore when read 001 4 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ro ignore when read 0 3 auto-negotiation indication ro 1 = auto-negotiation activated 0 = speed forced manually 1 2 force 100/10 indication ro 1 = speed forced to 100base-x 0 = speed forced to 10base-t 1 1 speed indication ro 1 = 100base-x 0 = 10base-t 0 0 full-duplex indication ro 1 = full-duplex active 0 = full-duplex not active 0 note: all error bits in the auxiliary error and general status register are read-only and are latched high. when certain types of errors occur in the bcm5201, one or more corresponding error bits become ?1?. they remain so until the register is read, or until a chip reset occurs. all such errors necessarily result in data errors, and are indicated by a high value on the rxer output pin at the time the error occurs. notes: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 50 auxiliary mode register document 5220-ds04-405-r when bit 2 of the auxiliary control register is 0, the speed of the chip is 10base-t. in all other cases, either the speed is not forced (auto-negotiation is enabled), or the speed is forced to 100base-x. speed indication this read-only bit shows the true current operation speed of the bcm5220. a 1 bit indicates 100base-x operation, while a 0 indicates 10base-t. while the auto-negotiation exchange is performed, the bcm5220 is always operating at 10base-t speed. full-duplex indication this read-only bit returns a 1 when the bcm5220 is in full-duplex mode. in all other modes, it returns a 0. a uxiliary m ode r egister table 28 shows the bit descriptions for the auxiliary mode register. activity led disable when set to 1, disables the xmtled# and rcvled# output pins. when 0, xmtled# and rcvled# output pins are enabled. link led disable when set to 1, disables the link led output pin. when 0, link led output is enabled. table 28: auxiliary mode register (address 29d, 1dh) bit name r/w description default 15:13 reserved a ro ignore when read 12 alternative link led mode r/w 1 = lnkled# indicates link at 100base-tx, spdled# indicates link at 10base-t. 0 = normal operation for lnkled# and spdled#. 0 11:5 reserved a ro ignore when read 0 4 activity led disable r/w 1 = disable xmt/rcv activity led outputs 0 = enable xmt/rcv activity led outputs 0 3 link led disable r/w 1 = disable link led output 0 = enable link led output 0 2 reserved a ro ignore when read 1 block txen mode r/w 1 = enable block txen mode 0 = disable block txen mode 0 0 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? ro ignore when read 0
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auxiliary multiple phy register page 51 block txen mode when this mode is enabled, short ipgs of 1, 2, 3 or 4 txc cycles results in the insertion of two idles before the beginning of the next packet?s jk symbols. a uxiliary m ultiple phy r egister hcd bits bits 15:11 of the auxiliary multiple phy register are 5 read-only bits that report the highest common denominator (hcd) result of the auto-negotiation process. immediately upon entering the link pass state after each reset or restart auto- negotiation, only 1 of these 5 bits is 1. the link pass state is identified by a 1 in bit 6 or 7 of this register. the hcd bits are reset to 0 every time auto-negotiation is restarted or the bcm5220 is reset. for their intended application, these bits uniquel y identify the hcd only after the first link pass after reset or restart of auto-negotiation. on later link fault and subsequent re- negotiations, if the ability of the link partner is different, more than 1 of the above bits can be active. table 29: auxiliary multiple phy register (address 30d, 1eh) bit name r/w description default 15 hcd_tx_fdx ro 1 = auto-negotiation result is 100base-tx full-duplex 0 14 hcd_t4 ro 1 = auto-negotiation result is 100base-t4 0 13 hcd_tx ro 1 = auto-negotiation result is 100base-tx 0 12 hcd_10base-t_fdx ro 1 = auto-negotiation result is 10base-t full-duplex 0 11 hcd_10base-t ro 1 = auto-negotiation result is 10base-t 0 10:9 reserved a ro ignore when read 00 8 restart auto-negotiation r/w (sc) 1 = restart auto-negotiation process 0 = (no effect) 0 7 auto-negotiation complete ro 1 = auto-negotiation process completed 0 = auto-negotiation process not completed 0 6 acknowledge complete ro 1 = auto-negotiation acknowledge completed 0 5 acknowledge detected ro 1 = auto-negotiation acknowledge detected 0 4 ability detect ro 1 = auto-negotiation waiting for lp ability 0 3 super isolate r/w 1 = super isolate mode 0 = normal operation 0 2 reserved a ro ignore when read 0 1 10base-t serial mode r/w 1 = enable 10base-t serial mode 0 = disable 10base-t serial mode 0 0 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? r/w write as 0, ignore when read 0 notes: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 52 auxiliary multiple phy register document 5220-ds04-405-r restart auto-negotiation this self-clearing bit allows the auto-negotiation process to be restarted, regardless of the current status of the state machine. for this bit to work, auto-negotiation must be enabled. writing a 1 to this bit restarts auto-negotiation. since the b it is self-clearing, it always returns a 0 when read. the operation of this bit is identical to bit 9 of the control register. auto-negotiation complete this read-only bit returns a 1 after the auto-negotiation process has been completed. it remains 1 until the auto-negotiation process is restarted, a link fault occurs, or the chip is reset. if auto-negotiation is disabled or the process is still in pro gress, the bit returns a 0. acknowledge complete this read-only bit returns a 1 after the acknowledgment exchange portion of the auto-negotiation process has been completed and the arbitrator state machine has exited the complete acknowledge state. it remains this value until the auto- negotiation process is restarted, a link fault occurs, auto-negotiation is disabled, or the bcm5220 is reset. acknowledge detected this read-only bit is set to 1 when the arbitrator state machine exits the acknowledged detect state. it remains high until the auto-negotiation process is restarted, or the bcm5220 is reset. ability detect this read-only bit returns a 1 when the auto-negotiation state machine is in the ability detect state. it enters this state a specified time period after the auto-negotiation process begins, and exits after the first flp burst or link pulses are detecte d from the link partner. this bit returns a 0 any time the auto-negotiation state machine is not in the ability detect state. super isolate writing a 1 to this bit places the bcm5201 into the super isolate mode. additionally, all link pulses are suppressed. this allows the bcm5201 to coexist with another phy on the same adapter card, with only one being activated at any time. 10base-t serial mode writing a 1 to bit 1 of the auxiliary mode register enables the 10base-t serial mode. in the special 10base-t serial mode, data packets traverse to the mac layer across only txd0 and rxd0 at a rate of 10 mhz. serial operation is not available in 100base-x mode.
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auxiliary multiple phy register page 53 b roadcom t est r egister shadow register enable writing a 1 to bit 7 of register 1fh allows r/w access to the shadow registers. table 30: broadcom test (address 31d, 1fh) bit name r/w description default 15:8 reserved a ro ignore when read 00h 7 shadow register enable r/w 1 = enable shadow registers 0 = disable shadow registers 0 6 reserved a ro ignore when read 0 5 reserved a r/w write as 0, ignore when read 0 4:0 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? r/w write as 0bh, ignore when read 0bh notes: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s).
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 54 auxiliary multiple phy register document 5220-ds04-405-r a uxiliary m ode 4 r egister (s hadow r egister ) force led [1:0] the spdled#, lnkled#, xmtled#, rcdled#, col_led#, act_led# and fdx_led# outputs can be forced to on state (0) by writing a value of 01 to force led [1:0]. these leds can be forced to off state (1) by writing a value of 10 to force led {1:0]. enable clock during low power if this bit is set to a 1 then the clocks are running in low mode. force iddq mode. if this bit is set to a 1, then the bcm5220 enters iddq mode. when the device is in iddq mode, everything is disabled. the bcm5220 requires a hard reset to return to normal mode. table 31: auxiliary mode 4 register (shadow register 26d, 1ah) bit name r/w description default 15:6 reserved a r/w write as 30h, ignore when read 30h 5:4 force led [1:0] r/w 01 = force all led status to on 0 state 10 = force all led status to off 1 state 00 3 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? r/w write as 0, ignore when read 0 2 enable clock during low power r/w 0 = disables clock during low power modes 1 = enables clock during low power modes 0 1 force low power mode r/w 0 = normal operation 1 = forces the 5220 to enter the low power mode 0 0 force iddq mode r/w 0 = normal operation 1 = causes the bcm5220 to go to iddq mode 0 notes: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1.
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auxiliary multiple phy register page 55 a uxiliary s tatus 2 r egister (s hadow r egister ) mlt3 detected the bcm5220 returns a 1 in this bit whenever mlt3 signaling is detected. apd enable when in normal mode, if this bit set to a 1, the bcm5220 enters auto power down mode. if this bit is set, the bcm5220 enters low power mode whenever the link is lost. when energy is detected the device enters full power mode. otherwise, it wakes- up after 2.5s or 5.0s, as determined by the apd sleep timer bit. when the bcm5220 wakes up, it sends link pulses and monitors energy. if the link partner?s energy is detected then the bcm5220 enters full power mode and establishes a link with the link partner. if no energy is detected from the link par tner, it continues to stay in wake-up mode for a duration determined by the apd wake-up timer before going to low power mode. apd sleep timer this bit determines how long the bcm5220 stays in low power mode before wake-up. if this bit is a 0, then it waits approximately 2.5s before wake-up, else 5s. apd wake-up timer [3:0] this counter determines how long the bcm5220 stays up in wake-up mode before going to low-power mode. this value is specified in 40-ms increments from 0 to 600 ms. a value of 0 forces the bcm5220 to stay in low-power mode indefinitely. in this case the bcm5220 requires a hard reset to return to normal mode. table 32: auxiliary status 2 register (shadow register 27d, 1bh) bit name r/w description default 15 mlt3 detected r/o 1 = mlt3 detected 0h 14:6 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? r/o 000h 5 apd enable r/w 0 = normal mode 1 = enable auto power down mode 0 4 apd sleep timer r/w 0 = 2.5 sec sleep before wake-up 1 = 5.0 sec sleep before wake-up 0 3:0 apd wake-up timer [3:0] r/w duration of wake-up 0001 notes: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1.
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 56 auxiliary status 3 register (shadow register) document 5220-ds04-405-r a uxiliary s tatus 3 r egister (s hadow r egister ) noise [7:0] the bcm5220 provides the current mean squared error value for noise when a valid link is established. fifo consumption [3:0] the bcm5220 indicates the number of nibbles of fifo currently used. a uxiliary m ode 3 r egister (s hadow r egister ) table 33: auxiliary status 3 register (shadow register 28d, 1ch) bit name r/w description default 15:4 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? r/w write as 000h, ignore when read 000h 3:0 fifo consumption [3:0] r/o currently utilized number of nibbles in the receive fifo 0000 mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1 table 34: auxiliary mode 3 register (shadow register 29d, 1dh) bit name r/w description default 15:9 reserved a r/w write as 00h, ignore when read 0 8 reserved a r/w write as 0, ignore when read 0 7 reserved a r/w write as 0, ignore when read 0 6 reserved a r/w write as 0, ignore when read 0 5:4 reserved a a. preserve existing values of reserved bi ts by completing a ?read/modify write.? r/w write as 00, ignore when read 0h 3:0 fifo size select [3:0] r/w currently selected receive fifo size 4h notes: r/w = read/write, ro = read only, sc = self clear, ll = latched low, lh = latched high, ll & lh clear after read operation. use default values of reserved bit(s) when writing to reserved bit(s). mii shadow register bank 1 is accessed by setting mii register 1fh bit 7 to a 1.
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auxiliary status 4 register (shadow register) page 57 fifo size select [3:0] the bcm5220 indicates the current selection of receive fifo size using bit 3 through 0 as shown in table 35. a uxiliary s tatus 4 r egister (s hadow r egister ) packet length counter [15:0] the bcm5220 shows the number bytes in the last packet received. this is valid only when a valid link is established. table 35: current receive fifo size fifo size select [3:0] receive fifo size in use (# of bits) 0001 16 0010 20 0011 24 0100 28 0101 32 0110 36 0111 40 1000 44 1001 48 1010 52 1011 56 1100 60 1101 64 table 36: auxiliary status 4 register (shadow register 30d, 1eh) bit name r/w description default 15:0 packet length counter[15:0] r/o number of bytes in the last received packet 0000h
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 58 auxiliary status 4 register (shadow register) document 5220-ds04-405-r section 6: timing an d ac characteristics the timing information contained in this section applies to the bcm5220. all mii interface pins comply with ieee 802.3u timing specifications (see reconciliation sublayer and media independent interface in ieee 802.3u timing specifications). all digital output timing specified at c l = 30 pf. output rise/fall times measured between 10% and 90% of the output signal swing. input rise/fall times measured between v il max. and v ih min. output signal transitions referenced to the midpoint of the output signal swing. input signal transitions referenced to the midpoint between v il max. and v ih min. see table 37 and table 38 for the timing parameters. see figure 3 for an illustration of clock and reset timing. table 37: clock timing parameter symbol min typ max unit xtali cycle time ck_cycle 39.998 40 40.002 ns xtali high/low time ck_hi ck_lo 14 20 26 ns ref_clk cycle time (mii - 25 mhz) 40 ns ref_clk high/low time (mii - 25 mhz) 13 20 27 ns ref_clk rise/fall time (mii - 25 mhz) 4 ns ref_clk cycle time (rmii - 50 mhz) 20 2 ns ref_clk high/low time (rmii - 50 mhz) 7 10 13 ns ref_clk rise/fall time (rmii - 50 mhz) 2 ns table 38: reset timing parameter symbol min typ max unit reset pulse length with stable xtali input (see note) reset_len 400 ns activity after end of hardware reset reset_wait 100 s reset# rise/fall time reset_edge 10 ns note: d uring power-on, reset# pin must be held low to get the bcm5220 to power-up in normal mode.
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auxiliary status 4 register (shadow register) page 59 figure 3: clock and reset timing table 39 provides the parameters for 100base-x transmit ti ming. figure 4 illustrates the 100base-tx transmit start of packet timing and figure 5 on page 60 shows the100base-tx transmit end of packet timing. table 39: mii 100base-x transmit timing parameter symbol min typ max unit txc cycle time 40 ns txc high/low time 16 20 24 ns txc rise/fall time 2 5 ns txen, txd[3:0] setup time to txc rising txen_setup 10 ns txen, txd[3:0] hold time from txc rising txen_hold 0 ns td after txen assert (unsampled) txen_tdata 100 ns txd to td steady state delay txd_tdata 100 ns crs assert after txen assert txen_crs 11 ns crs deassert after txen deassert txen_crs_eop 11 ns col assert after txen assert (while rx) txen_col 17 ns col deassert after txen deassert (while rx) txen_col_eop 17 ns xtali reset# normal phy reset_len reset_wait ck_hi ck_cycle ck_edge ck_lo ck_edge activity begins here reset_edge reset_edge
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 60 auxiliary status 4 register (shadow register) document 5220-ds04-405-r figure 4: mii transmit start of packet timing (100base-tx) figure 5: mii transmit end of packet timing (100base-tx) table 40 below provides 10base-x receive timing parameters. see figure 6 on page 61 and figure 7 on page 62 for illustrations of 100base-tx receive start of packet timing parameters and 100base-tx receive end of packet timing. figure 8 on page 62 shows 100base-tx receive packet premature end. see figure 9 on page 63 for an illustration of link failure or stream cipher error during receive packe t. 100base-tx false carrier sense timing is shown in figure 10 on page 63. 5 55 5 tx_tdata txen_crs txen_col txd_tdata ssd 3rd data nibble col * * when receive is concurrently active ii iij4 j3 j2 k4 k3 k2 k1 k0 crs td txer txen txd, j1 txen_setup i i i i i i i i i x j0 txen_hold xtali or txc esd txen_crs_eop txen_col_eop last data data n t4 t3 t2 t1 t0 r4 r3 r2 r1 r0 nibble td txd, txer col txen crs i i i i x xtali or txc
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auxiliary status 4 register (shadow register) page 61 figure 6: mii receive start of packet timing (100base-tx) table 40: mii 100base-x receive timing parameter symbol min typ max unit rxc cycle time 40 ns rxc high/low time (rxdv asserted) 20 ns rxc high time (rxdv deasserted) 20 ns rxc low time (rxdv deasserted) 20 ns rxc rise/fall time 2 5 ns rxdv, rxer, rxd[3:0] delay from rxc falling -4 4 ns crs deassert from rxc falling (valid eop only) 1 ns crs assert after rd rx_crs 130 ns crs deassert after rd (valid eop) rx_crs_eop 170 ns crs deassert after rd (premature end) rx_crs_idle 165 ns rxdv assert after rd rx_rxdv 165 ns rxdv deassert after rd ( valid eop) rx_rxdv_eop 170 ns rxdv assert after crs 40 ns rd to rxd steady state delay rx_rxd 170 ns col assert after rd (while tx) rx_col 125 ns col deassert after rd (valid eop) rx_col_eop 175 ns col deassert after rd (premature end) rx_col_idle 165 ns note: rxc minimum high and low times are guaranteed when rxen is asserted or deasserted. the mii port will always tristate while rxen is low. rx_crs rx_col 3rd data ssd rx_rxdv nibble * when transmit is active j4 j3 j2 k4 k3 k2 k1 k0 j1 j0 ii ii i i i 0 5 col* rxdv rxd, rd rxc crs rxer rxc_max_hi rxc_max_lo
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 62 auxiliary status 4 register (shadow register) document 5220-ds04-405-r figure 7: mii receive end of packet timing (100base-tx) figure 8: mii receive packet premature end (100base-tx) last data col rxdv rxd, rd rxc crs esd rx_crs_eop rx_col_eop n4 n3 n2 n1 n0 t4 t3 t2 t1 t0 r4 r3 r2 r1 r0 rxer nibble data n rx_rxd i i i i i i i i i i rx_rxdv_eop 0 rxen data i rxdv rxd rd rxc crs ii ii i i ii ii i i i i ii ii i i data error code (6) rx_crs_idle rx_col_idle rxer 0
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auxiliary status 4 register (shadow register) page 63 figure 9: mii link failure or stream cipher error during receive packet figure 10: mii false carrier sense timing (100base-tx) table 41 provides the parameters for 10base-t transmit timi ng. figure 11 illustrates 10base-t transmit start of timing packet. table 41: mii 10base-t transmit timing parameter symbol min typ max unit txc cycle time (10base-t) txc_cycle 395 400 405 ns note : txd, txen delivered to the bcm5220 should be generated of the rising edge of txc. rxdv rxd rxc crs data error code (2 or 3) rxer link/ lock 0 0 rxdv rxd rd rxc crs rxer 0 e i i ii i i ii ii i i ii i i i i i i
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 64 auxiliary status 4 register (shadow register) document 5220-ds04-405-r figure 11: mii 10base-t transmit start of packet timing table 42 provides the parameters for mii 10base-t receive timing. mii 10base-t collision timing is shown in table 43. txc high/low time (10base-t) 197.5 200 202.5 ns txc rise/fall time 2 5 ns txc rising edge to txen valid txc_txen_valid 25 ns txc rising edge to txen hold txc_txen_hold 75 ns txc rising edge to txd valid txc_txd_valid 25 ns txc rising edge to txd hold txc_txd_hold 75 ns td after txen assert txen_tdata 400 ns crs assert after txen assert txen_crs 60 ns crs deassert after txen deassert txen_crs_eop 60 ns idle on twisted pair after txen de-assert (sampled) tx_quiet 400 ns table 42: mii 10base-t receive timing parameter symbol min typ max unit rxc cycle time rxc_cycle 400 ns table 41: mii 10base-t transmit timing parameter symbol min typ max unit note : txd, txen delivered to the bcm5220 should be generated of the rising edge of txc. txc txen txc_txen_valid txc_txen_hold 10base-t mii input latch point 50 ns 5 txd crs txen_crs txc_txd_hold txc_txd_valid 400 ns
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auxiliary status 4 register (shadow register) page 65 table 44 provides the parameters for 10base-t serial transmit timing. figure 12 illustrates 10base-t serial transmit start of timing packet. rxc high/low time 200 ns crs assert after receive analog data rx_crs_bt 230 ns rxc valid after crs assert rxc_valid 1.7 s rxdv assert after receive analog data rx_rxdv 1.2 s rxdv deassert after receive analog eop ends rx_not_rxdv 400 ns crs deassert after receive analog eop ends rx_not_crs 400 ns table 43: mii 10base-t collision timing parameter symbol min typ max unit col assert after receive analog (while transmitting) rx_col 220 ns col deassert after txen deassert (while receiving) txen_not_col 400 ns col assert after txen assert (while receiving) txen_col 50 ns col deassert after receive analog ends (while transmitting) rx_not_col 200 ns table 44: 10base-t serial transmit timing parameter symbol min typ max unit txc cycle time txc 95 100 105 ns txc low time txc high time txc_lo txc_high 97.5 102.5 ns txc rise time txc fall time txc_rise txc_fall 25ns txen, txd0 to txc rising txen_setup 10 ns txen, txd0 hold after txc rising txen_hold 0 ns txen to td+ start txen_tdata 350 ns txen to td+ end txen_quiet 400 ns table 42: mii 10base-t receive timing parameter symbol min typ max unit
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 66 auxiliary status 4 register (shadow register) document 5220-ds04-405-r figure 12: 10base-t serial transmit timing table 45 provides the parameters for 10base-t serial receive timing. figure 13 illustrates 10base-t serial receive start of timing packet. table 45: 10base-t serial receive timing parameter symbol min typ max unit rxc to rxd0 output delay rxd_delay 5 ns crs assert after rd rx_crs_dv 220 ns crs deassert after rd , valid eop rx_not_crs 270 ns txc_low txc_high txc_rise txc_fall txc txen txen_setup txen_hold txen_quiet txen_txdata txen_setup txen_hold td+/-
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auxiliary status 4 register (shadow register) page 67 figure 13: 10base-t serial receive timing table 46, table 47, and table 48 provide the parameters for loopback timing, auto-negotiation timing, and led timing. table 46: loopback timing (mii) parameter symbol min typ max unit txd to rxd steady state propagation delay 184 ns table 47: auto-negotiation timing parameter symbol min typ max unit link test pulse width 100 ns flp burst interval 16 ms clock pulse to clock pulse 123 s clock pulse to data pulse (data = 1) 62.5 s table 48: led timing parameter symbol min typ max unit led on time (xmtled#, rcvled#, actled#) 80 ms led off time (xmtled#, rcvled#, actled#) 80 ms rxc rxd0 rxd_delay rd+/- rx_crs_bt rx_rxdv rx_not_crs
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 68 auxiliary status 4 register (shadow register) document 5220-ds04-405-r management data interface timing parameters are described in table 49. figure 14 and figure 15 illustrate two types of management interface timing. figure 14: management interface timing figure 15: management interface timi ng (with preamble suppression on) table 49: management data interface timing parameter symbol min typ max unit mdc cycle time 40 ns mdc high/low 20 ns mdc rise/fall time 10 ns mdio input setup time to mdc rising 10 ns mdio input hold time from mdc rising 10 ns mdio output delay from mdc rising 0 30 ns mdio (from bcm5220) mdc mdc_fall mdio_hold mdio_setup mdc_rise mdc_cycle mdio_setup mdio_hold mdio_delay mdio (into bcm5220 ) mdc skip skip d0 d1 hi-z (phy pull-up) idle s t mdio start of mdc/mdio cycle end of mdc/mdio cycle note: must wait two mdc clock cycles between mdio commands when preamble suppression is activated (mii register 1, bit 6 set to 1).
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auxiliary status 4 register (shadow register) page 69 rmii transmit timing parameters are described in table 50 and figure 16 illustrates the rmii management transmit timing. figure 16: rmii transmit packet timing rmii receive timing parameters are described in table 51 and figure 17 illustrates the rmii management receive timing. table 50: rmii transmit timing parameter symbol min typ max unit ref_clk cycle time 20 ns txen, txer, txd[1:0] setup time to ref_clk rising txen_setup 4 ns txen, txer, txd[1:0] hold time from ref_clk rising txen_hold 2 ns notes : 1. txd[1:0] provides valid data for each ref_clk period while tx_en is asserted. 2. as the ref_clk frequency is 10 times the data rate in 10mbps mode, the value on txd[1:0] is valid so that txd[1:0] can be sampled every 10 th cycle, regardless of the starting cycle within the group, and yield the correct frame data. table 51: rmii receive timing parameter symbol min typ max unit ref_clk cycle time 20 ns rxd[1:0], rxer, crs_dv output delay from ref_clk rising 216ns notes : 1. as the ref_clk frequency is 10 times the data rate in 10-mbps mode, the value on rxd[1:0] is valid so that rxd[1:0] can be sampled every 10 th cycle, regardless of the starting cycle within the group, and yield the correct frame data. 2. the receiver accounts for differences between the local ref_clk and the recovered clock through use of sufficient elasticity buffering. 3. the output delay is with a load of 25 pf, which accommodates a pcb trace length of over 12 inches. 0 0 0 0 0 0 0 0 txd[1] txd[0] tx_en ref_clk 1 1 1 1 1111111111 xxxx xx x x x x x x 00000000 preamble data sfd
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 70 auxiliary status 4 register (shadow register) document 5220-ds04-405-r figure 17: rmii receive packet timing table 52 describes the rmii 100base-x propagation delay timing parameters, and table 53 describes the rmii 10base-t propagation delay timing parameters. table 52: rmii 100base-x propagation delay timing parameter symbol min typ max unit td after txen assert txen_tdata 89 ns txd to td steady state delay txd_tdata 95 ns crs_dv assert after rd rx_crs_dv 124 ns crs_dv deassert after rd , premature end rx_crs_dv 164 ns crs_dv deassert after rd , valid eop rx_crs_dv_eop 237 ns table 53: rmii 10base-t propagation delay timing parameter symbol min typ max unit td after txen assert (sampled) txen_tdata 585 ns crs_dv assert after rd rx_crs_dv 220 ns /j/ /k/ preamble sfd data 0 1 0 0 00 0 0 0 0 0 0 0 0 0000000 111111xx xxx0 0 x xxxxx x 1 rxd[1] rxd[0] crs_dv ref_clk
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auxiliary status 4 register (shadow register) page 71 section 7: electrical characteristics table 54 provides the absolute maximum ratings for the bcm5220. the recommended operating conditions for the bcm5220 are shown in table 55. table 56 on page 71 gives the electrical characteristics of the bcm5220. table 54: absolute maximum ratings symbol parameter min max units v dd supply voltage regdvdd, regavdd, ovdd gnd - 0.3 3.60 v dvdd, avdd, biasvdd gnd - 0.3 2.75 v v i input voltage gnd - 0.3 ovdd + 0.3 v i i input current 10 ma t stg storage temperature ? 40 +125 c note : these specifications indicate levels where permanent damage to the device may occur. functional operation is not guaranteed under these conditions. operation at absolute maximum conditions for extended periods may adversely affect long-term reliability of the device. table 55: recommended operating conditions for bcm5220 symbol parameter pin operating mode min max units v dd supply voltage bcm5220 regdvdd, regavdd, ovdd 3.00 3.60 v dvdd, avdd, biasvdd 2.375 2.625 v v ih high-level input voltage all digital inputs 2.0 ovdd v v il low-level input voltage all digital inputs 0.8 v sd 100base-tx 0.4 v v idiff differential input voltage rd , sd 100base-fx 150 mv v icm common mode input voltage rd 100base-tx 1.85 2.05 v rd , sd 100base-fx 1.85 2.05 v t a ambient operating temperature 0 70 c table 56: electrical characteristics symbol parameter pins conditions min typ max units i dd supply current avdd, dvdd, ovdd 100base-tx 110 ma i dd supply current low power mode avdd, dvdd, ovdd clock on energy det on 12 ma i ddq supply current power off mode avdd, dvdd, ovdd hardware/software 3 ma
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 72 auxiliary status 4 register (shadow register) document 5220-ds04-405-r v oh high-level output voltage all digital outputs i oh = ? 12 ma ovdd- 0.5 v td driving loaded magnetics module avdd+1. 5 v v ol low-level output voltage all digital outputs i ol = 8 ma 0.4 v td driving loaded magnetics module avdd- 1.5 v v odiff differential output voltage td 100base-fx mode 400 mv i i input current digital inputs w/ pull-up resistors v i = ovdd +100 a v i = dgnd -200 a digital inputs w/ pull-down resistors v i = ovdd +200 a v i = dgnd -100 a all other digital inputs dgnd v i ovdd 100 a i oz high- impedance output current all three-state outputs dgnd v o ovdd a all open-drain outputs v o = ovdd a v bias bias voltage rdac 1.18 1.30 v table 56: electrical characteristics (cont.) symbol parameter pins conditions min typ max units
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auxiliary status 4 register (shadow register) page 73 section 8: application example figure 18: power connections bcm5220 (3.3v) bcm5220 digital bypass analog bypass regavdd regdvdd avdd dvdd ovdd .1uf 2.2uf .01uf 3.3v supply .1uf 2.2uf .01uf
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 74 auxiliary status 4 register (shadow register) document 5220-ds04-405-r section 9: thermal characteristics theta jc for this package in still air is 21.23 oc/w. the bcm5220kpb is designed and rated for a maximum junction temperature of 125 oc. theta jc for this package in still air is 18.5oc/w. the BCM5220KPT is designed and rated for a maximum junction temperature of 125oc. table 57: theta-j a vs. airflow for the bcm5220kpb (fbga 64) airflow (feet per minute) 0 100 200 400 600 theta - j a (oc/w) 35.15 25.57 22.99 20.88 20.30 table 58: theta-j a vs. airflow for the BCM5220KPT (64 tqfp) airflow (feet per minute) 0 100 200 400 600 theta - j a (oc/w) 56.4 51.9 49.9 48.2 47.2
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auxiliary status 4 register (shadow register) page 75 section 10: mechanical information figure 19: 64-pin tqfp 10mm package (bcm5220 kpt) seating plane a a1 a2 l b e r 1 2 r 2 1 c 1. drawings on this page are not to scale 2. all dimensions are in millimeters except where noted 3. foot length "l" is measured at gage plane, 0.25mm above the seating plane 4. seating plane is defined by three lowest lead tips 64-pin detail tqfp 10mm 3 4 h millimeter symbol min nom max a a1 a2 d d1 e e1 l e b c 0.05 1.35 11.80 9.90 11.80 0.50 0.50 0.17 0.22 0.27 0.60 0.75 12.00 12.20 10.00 10.10 12.00 12.20 1.40 1.45 0.15 1.60 0.17 h 0.08 r r 0.20 0.20 3 1 2 4 2 0 6 7 12 12 10 notes: 1 2 9.90 10.00 10.10 d1 d e1 e 1
bcm5220 preliminary data sheet 04/20/04 broadcom corporation page 76 auxiliary status 4 register (shadow register) document 5220-ds04-405-r figure 20: fbga 64-pin package, 8 mm x 8 mm (bcm5220 kpb)
preliminary data sheet bcm5220 04/20/04 broadcom corporation document 5220-ds04-405-r auxiliary status 4 register (shadow register) page 77 section 11: ordering information part number package ambient temperature BCM5220KPT 64-pin tqfp 10 mm package -40 to 85 c bcm5220kpb fbga 64-pin 8 mm x 8 mm package -40 to 85 c
document 5220-ds04-405-r broadcom corporation 16215 alton parkway p.o. box 57013 irvine, ca 92619-7013 phone: 949-450-8700 fax: 949-450-8710 broadcom ? corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, f unction, or design. information furnished by broadcom corporation is believed to be accurate and reliable. however, broadcom corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any prod uct or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. bcm5220 preliminary data sheet 04/20/04

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